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TMS320F Datasheet(PDF) 26 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 389 page ![]() Architecture Summary 2-3 Architectural Overview Figure 2–1. TMS320C24x DSP Controller Functional Block Diagram 2 4 16 PDPINT 4 4 9 41 7 Quadrature Encoder Pulse (QEP) Capture/ Units Compare Timers Purpose General- Manager Event Generator Wait-State Software Interface Memory External Emulation JTAG Test/ Peripheral Bus Timer Watchdog Interface Communications Serial- Interface Peripheral Serial- Converter to-Digital Analog- 10–Bit Data Bus 3 Reset Digital Input/Output Interrupts 20 4 Module System-Interface Module Clock Program Bus B1/B2 DARAM B0 DARAM ROM or Flash EEPROM† Initialization Interrupts Control Memory Controller Program CPU ’C2xx Shifter Product PREG TREG Multiplier Shifter Output Accumulator ALU Shifter Input Registers Mapped Memory- Registers Auxiliary Registers Control Status/ ARAU Register Instruction †’C24x devices contains ROM: ’F24x devices contains Flash EEPROM. Watchdog 1 2 CAN Note: The number of PWMS/digital I/O, ADC channels, and peripheral modules are dependent upon the device family. |
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