TMS320F datasheet(79/389 Pages) TI

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Interrupts

5-15

Program Control

5.6

Interrupts

The ’C24x DSP supports both hardware and software interrupts. The hard-

ware interrupts INT1 – INT6, along with NMI, TRAP, and RS, provide a flexible

interrrupt scheme. The software interrupts offer flexibility to access interrupt

vectors using software instructions. Table 5–5,

’C24x Interrupt Locations and

Priorities, on page 5-15 shows the vectors supported by the DSP core. Since

most of the ’C24x DSPs come with multiple peripherals, the core interrupts

(INT1–IN6) are expanded using additional system or peripheral interrupt logic.

Although the core interrupts are the same, the peripheral interrupt structure

varies slightly among ’C240 and ’C24x class of DSP controllers. For details on

how these core interrupts are multiplexed to meet peripheral interrupt require-

ments, refer to

TMS320F/C240 DSP Controllers, Peripheral Library and Spe-

cific Devices, (literature number SPRU161), and TMS320F241,C242,F243

DSP Controllers, System, and Peripherals, (literature number SPRU276).

The maskable core interrupt structure is supported by two registers, IFR and

IMR. The core interrupt logic has a global interrupt enable bit in the ST register.

Details of these registers are presented in the tables and sections that follow.

Table 5–5. ’C24x Interrupt Locations and Priorities

K†

Vector

Location

Name

Priority

Function

1 (highest)

Hardware reset (nonmaskable)

INT1

Maskable interrupt level #1}

INT2

Maskable interrupt level #2}

INT3

Maskable interrupt level #3}

INT4

Maskable interrupt level #4}

INT5

Maskable interrupt level #5}

INT6

Maskable interrupt level #6}

Reserved

10h

INT8

–

User-defined software interrupt

† The K value is the operand used in an INTR instruction that branches to the corresponding inter-

rupt vector location.

‡ Maskable interrupts are customized for each ’C24x DSP device with additional interrupt

expansion logic.

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