TMS320F datasheet(25/389 Pages) TI

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Architecture Summary

2-2

2.1

Architecture Summary

A functional block diagram of the ’C24x DSP controller architecture is shown

in Figure 2–1 on page 2-3. The ’C24x DSP architecture is based on a modi-

fied Harvard architecture, which supports separate bus structures for program

space and data space. A third space, the input/output (I/O) space, is also avail-

able and is accessible through the

external bus interface. To support a large

selection of peripherals, a peripheral bus is used. The peripheral bus is

mapped to the data space and interfaced to the data bus through a special sys-

tem module. Thus, all the instructions that operate on the data space also op-

erate on all the peripheral registers.

Separate program and data spaces allow simultaneous access to program

instructions and data. For example, while data is multiplied, a previous product

can be added to the accumulator, and at the same time, a new address can

be generated. Such parallelism supports a set of arithmetic, logic, and bit-ma-

nipulation operations that can all be performed in a single machine cycle. The

’C24x also includes control mechanisms to manage interrupts, repeated op-

erations, and function/subroutine calls.

TMS320F Datasheet(PDF) 25 Page - Texas Instruments