TMS320F datasheet(45/389 Pages) TI

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4-1

Central Processing Unit

This chapter describes the ’C24x central processing unit (CPU) and its opera-

tions. Because of its parallel architectural design, the ’C24x CPU can perform

high-speed arithmetic operations within one instruction cycle.

Three fundamental sections of the CPU are presented (see Figure 4–1) along

with a description of the auxiliary register arithmetic unit (ARAU), which per-

forms arithmetic operations independently of the central arithmetic logic

section. The chapter concludes with a description of status registers ST0 and

ST1. These registers contain bits for determining processor modes, address-

ing pointer values, and indicating various processor conditions and arithmetic

logic results.

Topic

Page

4.1

Input Scaling Section

4-3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

Multiplication Section

4-5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

Central Arithmetic Logic Section

4-8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4

Auxiliary Register Arithmetic Unit (ARAU)

4-12

. . . . . . . . . . . . . . . . . . . . .

4.5

Status Registers ST0 and ST1

4-15

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6

External Memory Interface Operation

4-18

. . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 4

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