TMS320F datasheet(40/389 Pages) TI

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Data Memory

3-7

Memory and I/O Spaces

3.3.1

Data Page 0 Address Map

The data memory also includes the device’s memory-mapped registers

(MMR), which reside at the top of data page 0 (addresses 0000h–007Fh).

Note the following:

- The three registers that can be accessed with zero wait states are:

J Interrupt mask register (IMR)

J Global memory allocation register (GREG)

J Interrupt flag register (IFR)

- The test/emulation reserved area is used by the test and emulation sys-

tems for special information transfers.

Do Not Write to Test/Emulation Addresses

Writing to the test/emulation addresses can cause the device to

change its operating mode and, therefore, affect the operation of

an application.

- The scratch-pad RAM block (B2) includes 32 words of DARAM that pro-

vide for variable storage without fragmenting the larger RAM blocks,

whether internal or external. This RAM block supports dual-access opera-

tions and can be addressed via any data-memory addressing mode.

Table 3–1 shows the address map of data page 0.

Table 3–1. Data Page 0 Address Map

Address

Name

Description

0000h–0003h

–

Reserved

0004h

IMR

Interrupt mask register

0005h

GREG

Global memory allocation register

0006h

IFR

Interrupt flag register

0023h–0027h

–

Reserved

002Bh–002Fh

–

Reserved for test/emulation

0060h–007Fh

Scratch-pad RAM (DARAM B2)

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