TMS320F datasheet(83/389 Pages) TI

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CPU Interrupt Registers

5-19

Program Control

Bit 0

INT1. Interrupt 1 flag. This bit is the flag for interrupts connected to interrupt

level INT1.

0 = No INT1 interrupt is pending.

1 = At least one INT1 interrupt is pending. Write a 1 to this bit to clear it to

0 and clear the interrupt request.

5.7.2

Interrupt Mask Register (IMR)

The IMR is a 16-bit, memory-mapped register located at address 0004h in

data memory space. The IMR contains mask bits for all the maskable interrupt

levels (INT1–INT6). Neither NMI nor RS is included in the IMR; thus, IMR has

no effect on these interrupts.

You can read the IMR to identify masked or unmasked interrupt levels, and you

can write to the IMR to mask or unmask interrupt levels. To unmask an interrupt

level, set its corresponding IMR bit to 1. To mask an interrupt level, set its corre-

sponding IMR bit to 0. When an interrupt is masked, it is not acknowledged,

regardless of the value of the INTM bit. When an interrupt is unmasked, it is

acknowledged if the corresponding IFR bit is 1 and the INTM bit is 0. At reset,

the IMR bits are all set to 0, masking all the maskable interrupts.

The IMR is shown in Figure 5–6,

Interrupt Mask Register (IMR) on page 5-20.

Bit descriptions follow the figure.

TMS320F Datasheet(PDF) 83 Page - Texas Instruments