TMS320F datasheet(81/389 Pages) TI

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CPU Interrupt Registers

5-17

Program Control

5.7

CPU Interrupt Registers

There are two CPU registers for controlling interrupts:

- The interrupt flag register (IFR) contains flag bits that indicate when mask-

able interrupt requests have reached the CPU on levels INT1 through

INT6.

- The interrupt mask register (IMR) contains mask bits that enable or dis-

able each of the interrupt levels (INT1 through INT6).

5.7.1

Interrupt Flag Register (IFR)

The interrupt flag register (IFR), a 16-bit, memory-mapped register at address

0006h in data-memory space, is used to identify and clear pending interrupts.

The IFR contains flag bits for all the maskable interrupts.

When a maskable interrupt is requested, the flag bit in the corresponding con-

trol register is set to 1. If the mask bit in that same control register is also 1, the

interrupt request is sent to the CPU, setting the corresponding flag in the IFR.

This indicates that the interrupt is pending, or waiting for, acknowledgement.

You can read the IFR to identify pending interrupts and write to the IFR to clear

pending interrupts. To clear a single interrupt, write a 1 to the corresponding

IFR bit. All pending interrupts can be cleared by writing the current contents

of the IFR back into the IFR. A device reset clears all IFR bits.

The following events also clear an IFR flag:

- The CPU acknowledges the interrupt.

- The ’C24x is reset.

Notes:

1) To clear an IFR bit, you must write a 1 to it, not a 0.

2) When a maskable interrupt is acknowledged,

only the IFR bit is cleared

automatically. The flag bit in the corresponding control register is

not

cleared. If an application requires that the control register flag be

cleared, the bit must be cleared by software.

3) When an interrupt is requested by an INTR instruction and the corre-

sponding IFR bit is set, the CPU does not clear the bit automatically. If

an application requires that the IFR bit be cleared, the bit must be cleared

by software.

The IFR is shown in Figure 5–5; descriptions of the bits follow the figure.

TMS320F Datasheet(PDF) 81 Page - Texas Instruments