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External Memory Interface Operation

4-18

4.6

External Memory Interface Operation

Some of the ’24x DSP controller devices have an external memory interface.

This section explains the behavior of the ’24x external memory timings based

on the PS, DS, IS, BR, STRB, RD, LR, and R/W signals.

All bus cycles comprise integral numbers of CLKOUT cycles. One CLKOUT

cycle is defined to be from one falling edge of CLKOUT to the next falling edge

of CLKOUT. For full-speed, 0-wait-state operation, reads require one cycle. A

write immediately preceded by a read or immediately followed by a read re-

quires three cycles. (Refer to Figure 4–12 on page 4-18, Figure 4–13 on page

4-20, and Figure 4–14 on page 4-20 for read and write timing cycles.) These

timing models explain CPU and external memory signal behavior during back-

to-back write, without wait state, and with one wait state. External READY tim-

ings in ’C24x devices can be satisfied only if internal wait state is at least one.

Refer to the respective datasheet for specific timing values.

Figure 4–12. External Interface Operation for Read-Read-Write (Zero Wait States)

1-cycle read

Read

STRB

IS,DS,PS

R/W

DATA

ADDRESS

CLKOUT

3-cycle write

Write data

For read cycles, STRB goes low and ADDRESS becomes valid with the falling

edge of CLKOUT. For 0-wait-state read cycles, the RD{ signal goes low with

the rising edge of CLKOUT and then goes high at the next falling edge of

CLKOUT. For 1-wait-state (multicycle) read cycles, the RD stays low but goes

high with the falling edge of CLKOUT before the next cycle, even if the cycles

are contiguous. Read data is sampled at the rising edge of RD.

† In some devices (F240), the external RD is replaced with an inverted R/W signal.

TMS320F Datasheet(PDF) 62 Page - Texas Instruments