TMS320F datasheet(61/389 Pages) TI

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Status Registers ST0 and ST1

4-17

Central Processing Unit

Table 4–2. Bit Fields of Status Registers ST0 and ST1 (Continued)

Name

Description

OVM

Overflow mode bit. OVM determines how overflows in the CALU are handled. The SETC and

CLRC instructions set and clear this bit, respectively. An LST instruction can also be used to

modify OVM.

OVM = 0

Results overflow normally in the accumulator.

OVM = 1

The accumulator is set to either its most positive or negative value upon encounter-

ing an overflow. (See subsection 4.3.2,

Accumulator, on page 4-9.)

Product shift mode. PM determines the amount that the PREG value is shifted on its way to the

CALU or to data memory. Note that the content of the PREG remains unchanged; the value is

copied to the product shifter and shifted there. PM is loaded by the SPM and LST instructions.

The PM bits are cleared by reset.

PM = 00

The multiplier’s 32-bit product is passed to the CALU or to data memory with no shift.

PM = 01

The output of the PREG is left shifted one place (with the LSBs zero filled) before

being passed to the CALU or to data memory.

PM = 10

The output of the PREG is left shifted four bits (with the LSBs zero filled) before being

passed to the CALU or to data memory.

PM = 11

This mode produces a right shift of six bits, sign extended.

SXM

Sign-extension mode bit. SXM does not affect the basic operation of certain instructions. For

example, the ADDS instruction suppresses sign extension regardless of SXM. This bit is set by

the SETC SXM instruction, cleared by the CLRC SXM instruction, and may be loaded by the LST

instruction. SXM is set to 1 by reset.

SXM = 0

This mode suppresses sign extension.

SXM = 1

In this mode, data values that are shifted in the input shifter are sign extended before

they are passed to the CALU.

Test/control flag bit. The TC bit is set to 1 if a bit tested by BIT or BITT is a 1, if a compare condi-

tion tested by CMPR exists between the current auxiliary register and AR0, or if the exclusive-OR

function of the two MSBs of the accumulator is true when tested by a NORM instruction. The

conditional branch, call, and return instructions can execute, based on the condition of the TC bit.

The TC bit is affected by the BIT, BITT, CMPR, LST, and NORM instructions.

XF pin status bit

. This bit determines the state of the XF pin, which is a general-purpose output

pin. XF is set by the SETC XF instruction and cleared by the CLRC XF instruction. XF can also

be modified with an LST instruction. XF is set to 1 by reset.

TMS320F Datasheet(PDF) 61 Page - Texas Instruments

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