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TMS320F Datasheet(PDF) 82 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 82 Page - Texas Instruments |
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82 / 389 page  CPU Interrupt Registers 5-18 Figure 5–5. Interrupt Flag Register (IFR) — Address 0006h 15–6 5 4 3 2 1 0 Reserved INT6 INT5 INT4 INT3 INT2 INT1 0 R/W–x R/W1C–x R/W1C–x R/W1C–x R/W1C–x R/W1C–x Note: 0 = Always read as zeros, R = Read access, W1C = Write 1 to this bit to clear it, –n = Value after reset, x = Value un- changed by reset Bits 15–6 Reserved. These bits are always read as 0s. Bit 5 INT6. Interrupt 6 flag. This bit is the flag for interrupts connected to interrupt level INT6. 0 = No INT6 interrupt is pending. 1 = At least one INT6 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. Bit 4 INT5. Interrupt 5 flag. This bit is the flag for interrupts connected to interrupt level INT5. 0 = No INT5 interrupt is pending. 1 = At least one INT5 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. Bit 3 INT4. Interrupt 4 flag. This bit is the flag for interrupts connected to interrupt level INT4. 0 = No INT4 interrupt is pending. 1 = At least one INT4 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. Bit 2 INT3. Interrupt 3 flag. This bit is the flag for interrupts connected to interrupt level INT3. 0 = No INT3 interrupt is pending. 1 = At least one INT3 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. Bit 1 INT2. Interrupt 2 flag. This bit is the flag for interrupts connected to interrupt level INT2. 0 = No INT2 interrupt is pending. 1 = At least one INT2 interrupt is pending. Write a 1 to this bit to clear it to 0 and clear the interrupt request. |
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