TMS320F datasheet(96/389 Pages) TI

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Indirect Addressing Mode

6-12

6.3.4

Indirect Addressing Opcode Format

Figure 6–6 shows the format of the instruction word loaded into the instruction

following Figure 6–6.

Figure 6–6. Instruction Register Content in Indirect Addressing

NAR

ARU

8 MSBs

Bits 15 through 8 indicate the instruction type (for example,

LT) and also contain any information regarding data shifts.

Direct/indirect indicator. Bit 7 contains a 1 to define the ad-

dressing mode as indirect.

ARU

Auxiliary register update code. Bits 6 through 4 determine

whether and how the current auxiliary register is increm-

ented or decremented. See Table 6–2 below.

Next auxiliary register indicator. Bit 3 specifies whether

the instruction changes the ARP value.

N = 0

The content of the ARP remains unchanged.

N = 1

The content of NAR is loaded into the ARP, and

the old ARP value is loaded into the auxiliary

NAR

Next auxiliary register value. Bits 2 through 0 contain the

value of the next auxiliary register. NAR is loaded into the

ARP if N = 1.

Table 6–2. Effects of the ARU Code on the Current Auxiliary Register

ARU Code

Arithmetic Operation Performed on Current AR

No operation on current AR

Current AR – 1

→ current AR

Current AR + 1

→ current AR

Reserved

Current AR – AR0

→ current AR [reverse carry propagation]

Current AR – AR0

→ current AR

Current AR + AR0

→ current AR

Current AR + AR0

→ current AR [reverse carry propagation]

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