TMS320F datasheet(47/389 Pages) TI

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Input Scaling Section

4-3

Central Processing Unit

4.1

Input Scaling Section

A 32-bit input data-scaling shifter (input shifter) aligns the 16-bit value from

memory to the 32-bit central arithmetic logic unit (CALU). This data alignment

is necessary for data-scaling arithmetic, as well as aligning masks for logical

operations. The input shifter operates as part of the data path between pro-

gram or data space and the CALU; and therefore, requires no cycle overhead.

Described below are the input, output, and shift count of the input shifter.

Figure 4–2,

Block Diagram of the Input Scaling Section, can be used as a ref-

erence throughout the discussion.

Figure 4–2. Block Diagram of the Input Scaling Section

Input shifter (32 bits)

MUX

16 15

Input scaling

section

From data memory (DRDB)

From program memory (PRDB)

To CALU

Input. Bits 15 through 0 of the input shifter accept a 16-bit input from either of

two sources (see Figure 4–2):

- The data read bus (DRDB). This input is a value from a data memory loca-

tion referenced in an instruction operand.

- The program read bus (PRDB). This input is a constant value given as an

instruction operand.

Output. After a value has been accepted into bits 15 through 0, the input shifter

aligns the16-bit value to the 32-bit bus of the CALU as shown in Figure 4–2.

The shifter shifts the value left 0 to 16 bits and then sends the 32-bit result to

the CALU.

During the left shift, unused LSBs in the shifter are filled with 0s, and unused

MSBs in the shifter are either filled with 0s or sign extended, depending on the

value of the sign-extension mode bit (SXM) of status register ST1.

TMS320F Datasheet(PDF) 47 Page - Texas Instruments