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TMS320F Datasheet(PDF) 35 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 35 Page - Texas Instruments

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Overview of Memory and I/O Spaces
3-2
3.1
Overview of Memory and I/O Spaces
The ’C24x design is based on an enhanced Harvard architecture. The ’C24x
has multiple memory spaces accessible on three parallel buses: a program
address bus (PAB), a data-read address bus (DRAB), and a data-write ad-
dress bus (DWAB). Each of the three buses access different memory spaces
for different phases of the device’s operation. Because the bus operations are
independent, it is possible to access both the program and data spaces simul-
taneously. Within a given machine cycle, the CALU can execute as many as
three concurrent memory operations.
The ’C24x address map is organized into four individually selectable spaces:
- Program memory (64K words) contains the instructions to be executed,
as well as data used during program execution.
- Data memory (64K words) holds data used by the instructions.
- Global data memory (32K words) shares data with other devices or
serves as additional data space.
- Input/output (I/O) space (64K words) interfaces to external peripherals
and may contain on-chip registers.
These spaces provide a total address space of 224K words. The ’C24x in-
cludes on-chip memory to aid in system performance and integration, and nu-
merous addresses that can be used for external memory and I/O devices.
The advantages of operating from on-chip memory are:
- Higher performance than external memory (because the wait states re-
quired for slower external memories are avoided)
- Lower cost than external memory
- Lower power consumption than external memory
The advantage of operating from external memory is the ability to access a
larger address space.
The memory maps shown in Figure 3–1 are generic for all ’C24x devices; how-
ever, each device has its own set of memory maps. ’C24x devices are avail-
able with different combinations of on-chip memory and peripherals. You
should refer to the appropriate data sheet for details about a specific device.



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