TMS320F datasheet(187/389 Pages) TI

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Load Status Register

LST

7-87

Assembly Language Instructions

Figure 7–4. LST #1 Operation

8765

43210

ST0

ARP

OVM

INTM

↑

8765

43210

Data

↓

8765

43210

ST1

ARB

CNF

SXM

Status Bits

Affects

ARB, ARP, OV, OVM, DP, CNF, TC, SXM, C, XF, and PM

This instruction does not affect INTM.

Description

The specified status register (ST0 or ST1) is loaded with the addressed data-

memory value. Note the following points:

- The LST #0 operation does not affect the ARB field in the ST1 register,

even though a new ARP is loaded.

- During the LST #1 operation, the value loaded into ARB is also loaded into

ARP.

- If a next AR value is specified as an operand in the indirect addressing

mode, this operand is ignored. ARP is loaded with the three MSBs of the

value contained in the addressed data-memory location.

- Reserved bit values in the status registers are always read as 1s. Writes

to these bits have no effect.

The LST instruction can be used for restoring the status registers after subrou-

tine calls and interrupts.

Words

Cycles for a Single LST Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

2+pcode

SARAM

2, 3†

2+pcode

External

2+dsrc

3+dsrc+pcode

† If the operand and the code are in the same SARAM block

Cycles

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