TMS320F datasheet(219/389 Pages) TI

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Multiply Unsigned

MPYU

7-119

Assembly Language Instructions

Syntax

MPYU

dma

Direct addressing

MPYU

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

MPYU

dma

987

6543

210

dma

MPYU

ind [,ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

Unsigned (TREG)

× unsigned (data-memory address) → PREG

Status Bits

None

This instruction is not affected by SXM.

Description

The unsigned contents of TREG are multiplied by the unsigned contents of the

addressed data-memory location. The result is placed in the product register

(PREG). The multiplier acts as a signed 17

× 17-bit multiplier for this instruc-

tion, with the MSB of both operands forced to 0.

When another instruction passes the resulting PREG value to data memory

or to the CALU, the value passes first through the product shifter at the output

of the PREG. This shifter always invokes sign extension on the PREG value

when PM = 3 (right-shift-by-6 mode). Therefore, this shift mode should not be

used if unsigned products are desired.

The MPYU instruction is particularly useful for computing multiple-precision

products, such as when multiplying two 32-bit numbers to yield a 64-bit prod-

uct.

Words

Opcode

TMS320F Datasheet(PDF) 219 Page - Texas Instruments

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