TAS2120 datasheet(32/63 Pages) TI

32 / 63 page

The internally generated tone can be mixed with incoming audio stream, or can replace the input audio stream

and only tone signal is generated using INTERNAL_TONE_MIXING_EN register.

Table 6-26. Internal tone generator mixing options

INTERNAL_TONE_MIXING_EN

Configuration

Only internal tone is generated.

1(default)

Internally generated tone is mixed

with input audio data and played

together.

The tone generator can use external clock source like BCLK, or it can be generated using internal oscillator to

generate tone signals even with no external clock sources using INTERNAL_TONE_CLK_SEL register.

Table 6-27. Internal tone clock source selection

INTERNAL_TONE_CLK_SEL

Configuration

0 (default)

Tone generator uses external

clocks

Tone generator uses internal

oscillator

6.4.3 Digital Audio Serial Interface

The device provides a flexible Audio Serial Interface (ASI) port. The port can be configured to support a variety

of formats including stereo I2S, Left Justified, and TDM. Mono audio playback is available via the SDIN pin. The

SDOUT pin is used to transmit sample streams including PVDD voltage, VBAT voltage, die temperature, status

and audio for echo reference.

The TDM serial audio port supports up to 16 32-bit time slots at 44.1/48 kHz, 8 32-bit time slots at a 88.2/96

kHz sample rate and 4 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots

at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. The device automatically detects the

number of time slots and this does not need to be programmed. PCM data sampling rate and SBCLK to FSYNC

ratio detected on the TDM bus is reported back on the read-only register bits FS_RATE_DETECTED[2:0] and

FS_RATIO_DETECTED[3:0] respectively.

Table 6-28. PCM Data Sample Rate Detected

FS_RATE_DETECTED[2:0]

(Read Only)

Setting

000

Reserved

001

14.7 kHz / 16 kHz

010

22.05 kHz / 24 kHz

011

29.4 kHz / 32 kHz

100 (default)

44.1 kHz / 48 kHz

101

88.2 kHz / 96 kHz

110

176.4 kHz / 192 kHz

111

Error condition

A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START

RX_EDGE register bit. The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the

transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified

format and 1 for an I2S format.

The RX_SLEN[1:0] register bits set the length of the RX time slot to 16, 24 or 32 (default) bits. The length of

the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will

TAS2120

SLASFC6 – AUGUST 2024

www.ti.com

Submit Document Feedback

Product Folder Links: TAS2120

TAS2120 Datasheet(PDF) 32 Page - Texas Instruments

TAS2120 Datasheet(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL