TAS2120 datasheet(14/63 Pages) TI

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5.6 Timing Requirements (continued)

TA = 25 °C, VDD = IOVDD = 1.8 V (unless other wise noted)

MIN

NOM

MAX

UNIT

tH(SBCLK) SBCLK high period

tL(SBCLK) SBCLK low period

tSU(FSYNC

)

FSYNC setup time

tHLD(FSYN

FSYNC hold time

tSU(SDIN/

ICC)

SDIN/ICC setup time

tHLD(SDIN/

ICC)

SDIN/ICC hold time

td(SDO/

ICC-

SBCLK)

SBCLK to SDOUT/ICC delay : 50% of SBCLK to 50% of SDOUT

IOVDD=1.8V

td(SDO/

ICC-

SBCLK)

SBCLK to SDOUT/ICC delay : 50% of SBCLK to 50% of SDOUT

IOVDD=3.3V

tr(SBCLK) SBCLK rise time : 10 % - 90 % Rise Time

tf(SBCLK) SBCLK fall time : 90 % - 10 % Rise Time

5.7 Typical Characteristics

TA = 25℃, VBAT = 3.6V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12V (External PVDD mode enabled) ,

VDD=1.8 V, IOVDD=1.8 V, Load = 8Ω + 33μH, LBOOST = 1μH, FIN = 1kHz, Fs = 48kHz, Gain = 21dBV,

BST_ILIM (1S Boost mode) = 5.1A, BST_ILIM (2S Boost mode) = 4.1A, SDZ=1, Noise gate mode disabled,

Measured filter free with an Audio Precision with a 22Hz to 20kHz un-weighted bandwidth, unless otherwise

noted.

Output Power (W)

0.001

0.01

0.05

0.2

0.5 1

2 3 45 7 10 20

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

VBAT = 2.5 V

VBAT = 3.6 V

VBAT = 4.4 V

VBAT = 5.5 V

RL = 8 Ω

1S Battery Mode

Figure 5-1. THD+N vs Output Power

Output Power (W)

0.001

0.01

0.05

0.2

0.5 1

2 3 45 7 10 20

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

VBAT2S=4.7V

VBAT2S=7.2V

VBAT2S=8.4V

VBAT2S=10V

RL = 8 Ω

2S Battery Mode

Figure 5-2. THD+N vs Output Power

TAS2120

SLASFC6 – AUGUST 2024

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