TAS2120 datasheet(23/63 Pages) TI

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Table 6-12. Battery mode selection

SEL_VBAT_MODE[1:0]

Configuration

00 (default)

Voltage monitor on VBAT pin. 1S

mode of operation

Voltage monitor on VBAT_SNS

pin. 1S mode of operation

Voltage monitor on VBAT_SNS

pin. 2S mode of operation

Reserved

Table 6-13. VBAT pin bias voltage selector

VBAT_BIAS_SEL1

Configuration

0 (default)

VBAT pin biasing based on

VBAT_BIAS_SEL2 register

VBAT pin voltage is half of 2S

battery voltage

Table 6-14. VBAT pin bias voltage selector

VBAT_BIAS_SEL2[1:0]

Configuration

Reserved

01(default)

Minimum VBAT pin voltage >

2.9V

Minimum VBAT pin voltage >

3.3V

Minimum VBAT pin voltage >

3.7V

6.3.1.6 External PVDD Mode

The internal Boost of TAS2120 can be disabled by setting BST_EN register low. When the external PVDD

mode is used, the class-D amplifier is directly powered from the voltage source on PVDD pin. The device

configurations needs to be updated using PPC3 software to configure the device in required performance

configurations for external PVDD mode of operation.

6.3.2 Faults and Status

During power-up sequencing, the power-on-reset circuit (POR) monitors the VDD and IOVDD pins and holds

device in reset (including all the configuration registers) until the supplies are valid. Any supply voltage dip on

VDD or IOVDD below the UVLO voltage thresholds resets the device immediately along with all the register

configurations.

During operation modes, the device monitors internal device status and fault conditions and can notify the

host of error and status conditions using the IRQZ interrupt pin and internal I2C based interrupt registers. The

interrupt generation in IRQZ pin can be masked by configuring the corresponding Interrupt mask register bit.

Table 6-15 lists the different faults and interrupts that the device monitors and the corresponding configuration

bits to enable/disable the interrupt generation and reading the I2C interrupt status

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TAS2120

SLASFC6 – AUGUST 2024

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