TAS2120 datasheet(40/63 Pages) TI

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6.5 Programming

The device contains configuration registers and programming coefficients that can be set to the desired values

for a specific system and application use. These registers are called device control registers and are each eight

bits in width, mapped using a page scheme.

Each page contains 128 configuration registers. All key device configuration registers are stored in page 0,

which is the default page setting at power up and after a software reset. All programmable coefficient registers

are located in page 2, page 3 and later pages. The current page of the device can be switched to a new desired

page by using the PAGE[7:0] bits located in register 0 of every page.

6.5.1 I2C Control Interface

The device supports the I2C control protocol as a target device, and is capable of operating in standard mode,

fast mode, and fast mode plus. Device configuration and status are provided via the SDA and SCL pins using

the I2C protocol.

6.5.2 I2C Address Selection

The TAS2120 can operate using one of four selectable device addresses. I2C target addresses is defined as

the 7 MSBs followed by read/write bit. Table 6-46 below illustrates how to select the device I2C address and

the address corresponds to R/W bit set to 0 (ie ADDR[6:0],1b'0). The I2C address is detected by sampling the

address pins when SDZ pin is released or when device is reset using software reset bit.

Table 6-46. I2C Mode Address Selection

I2C TARGET

ADDRESS

AD2 PIN

AD1 PIN

0x80 (global address)

0x90

GND

0x92

GND

IOVDD

0x94

IOVDD

GND

0x96

IOVDD

The TAS2120 has a global 7-bit I2C address 0x40 (0x80 in 8-bit format with R/W bit set to 0). When enabled

the device will additionally respond to I2C commands at this address regardless of the address pins selected .

This is used to speed up device configuration when using multiple TAS2120 devices and programming similar

settings across all devices. The I2C ACK / NACK cannot be used during the multi-device writes since multiple

devices are responding to the I2C command. The I2C CRC function should be used to ensure each device

properly received the I2C commands. At the completion of writing multiple devices using the global address, the

CRC at I2C_CKSUM register should be checked on each device using the local address for a proper value. The

global I2C address can be disabled using I2C_GBL_EN register.

Table 6-47. I2C Global Address Enable

I2C_GBL_EN

SETTING

Disabled

Enabled (default)

6.5.3 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits

in a system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In

addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.

Each transfer operation begins with the controller device driving a start condition on the bus and ends with the

controller device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the

clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and

a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock

period.

TAS2120

SLASFC6 – AUGUST 2024

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