TAS2120 datasheet(33/63 Pages) TI

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left justify the audio sample within the time slot by default, but this can be changed to right justification via the

RX_JUSTIFY register bit. The device supports mono and stereo down mix playback ([L+R]/2). By default the

device will playback mono from the time slot equal to the I2C base address offset (set by the AD1 and AD2 pins)

for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot,

right time slot or stereo down mix set by the RX_SLOT_R[3:0] and RX_SLOT_L[3:0] register bits.

If time slot selection places reception either partially or fully beyond the frame boundary, the receiver returns a

null sample equivalent to a digitally muted sample.

The TDM port can transmit a number of sample streams on the SDOUT pin including interrupts and status,

PVDD voltage, VBAT voltage and die temperature.

Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin. This can be

configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK

cycles between the start of a frame and the beginning of time slot 0. This is programmed to 0 for Left Justified

format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the

TX_FILL register bit. An optional bus keeper can weakly hold the state of SDOUT pin when all devices are

driving Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPEN

TX_KEEPLN register bit. Additionally, the keeper LSB can be driven for a full cycle or half of cycle using

TX_KEEPCY register bit.

The device also support monitoring and TDM transmit of PVDD and VBAT input voltages. For PVDD slot,

enable and length settings PVDD_SLOT[5:0], PVDD_TX and PVDD_SLEN register bits can be use. Similarly

for VBAT slot, enable and length settings VBAT_SLOT[5:0], VBAT_TX and VBAT_SLEN register bits can be

used. Die temperature can also be transmitted from the device in same manner. Enable and slot settings for Die

temperature are done using TEMP_TX and TEMP_SLOT [5:0] register bits.

Information about status of slots can be found in STATUS_SLOT[5:0] register bits. STATUS_TX register bit set

high enables the status transmit. Status slot length is always 8bits and Table 6-29 summarizes the status bit

information that is transmitted when status transmit is enabled. If time slot selections place transmission beyond

the frame boundary, the transmitter will truncate transmission at the frame boundary.

Table 6-29. Status Bits transmitted

Status Slot bit location

Status signal

Bit 0

PVDD UVLO status bit

Bit 1

Over current protection status bit

Bit 2

Over temperature protection

status bit

Bit 3

Brown out protection active status

bit

Bit 4

Limiter active status bit

Bit 5

Noise gate mode status bit

Bit 6

Y-bridge status bit. 1 = PVDD

switching, 0 = VDD switching

Bit 7

Device Active status bit

6.4.3.1 Digital Loopback

The device supports loop back feature to loop SDIN data to SDOUT at two levels. When this feature is enabled

through TDM_LOOPBACK register bit, loop back is done at the IO Pin level without any ASI data decoding

within the device. Other option is to enable the loop back feature through TDM_DESER_LOOPBACK register

bit in which case SDIN data first goes through ASI protocol decoding within the device and then sent back via

SDOUT. These SDIN to SDOUT loop back options can be useful for board level debug of an audio system.

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TAS2120

SLASFC6 – AUGUST 2024

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