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TAS2120 Datasheet(PDF) 12 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 63 page  5.5 Electrical Characteristics (continued) TA = 25 °C, VBAT = 3.6 V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12 V ( External PVDD mode enabled), VDD = 1.8 V, IOVDD = 1.8V RL = 8Ω + 33µH, LBOOST = 1µH, fin = 1 kHz, fs = 48 kHz, Gain = 21dBV, BST_ILIM (1S battery) = 5.1A, BST_ILIM (2S battery, HW mode)=4.1A, BST_ILIM (2S battery, I2C mode)=5.1A, SDZ = 1, Noise gate disabled, Measured filter free with an Audio Precision using 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ_IDLE Current consumption in Idle Channel, , HW pin control mode VBAT, POUT = 0, Noise gate disabled mA VBAT2S, POUT = 0, Noise gate disabled mA VDD, POUT = 0, Noise gate disabled mA IOVDD, POUT = 0, Noise gate disabled mA Total Power, POUT = 0, Noise gate disabled mW Current Consumption - External PVDD Mode IQ_HW_SD Current consumption in Hardware Shutdown PVDD, SDZ=0 1 uA VBAT, SDZ=0 0.1 uA VDD, SDZ=0 0.2 uA IOVDD, SDZ=0 0.1 uA IQ_SW_SD Current consumption in Software Shutdown PVDD, All clocks Stopped 1 uA VBAT, All clocks Stopped 0.1 uA VDD, All clocks Stopped 12 uA IOVDD, All clocks Stopped 0.1 uA IQ_NG Current consumption in Idle channel PVDD, POUT = 0, Noise gate enabled 0.1 mA VBAT, POUT = 0, Noise gate enabled 0.15 mA VDD, POUT = 0, Noise gate enabled 2.2 mA IOVDD, POUT = 0, Noise gate enabled 0.1 mA Total Power, POUT = 0, Noise gate enabled 5.3 mW IQ_IDLE Current consumption in Idle channel PVDD, POUT = 0, Noise gate disabled 0.2 mA VBAT, POUT = 0, Noise gate disabled 0.5 mA VDD, POUT = 0, Noise gate disabled 5.6 mA IOVDD, POUT = 0, Noise gate disabled 0.1 mA Total Power, POUT = 0, Noise gate disabled 14.0 mW IQ_IDLE Current consumption in Idle channel, , HW pin control mode PVDD, POUT = 0, Noise gate disabled mA VBAT, POUT = 0, Noise gate disabled mA VDD, POUT = 0, Noise gate disabled mA IOVDD, POUT = 0, Noise gate disabled mA Total Power, POUT = 0, Noise gate disabled mW DIGITAL IOs VIH High-level digital input logic voltage threshold All digital pins 0.7 x IOVDD V VIL Low-level digital input logic voltage threshold All digital pins 0.3 x IOVDD V VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOH = 100µA IOVDD - 0.2 V V VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOL = -100µA 0.2 V VOL(I2C) Low-level digital output voltage SDA and SCL; IOL = -1mA 0.2 x IOVDD V TAS2120 SLASFC6 – AUGUST 2024 www.ti.com 12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAS2120 |
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