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TAS2120 Datasheet(PDF) 52 Page - Texas Instruments |
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TAS2120 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 63 page ![]() 8 Power Supply Recommendations TAS2120 supports supply voltages to ramp up/down in any order of sequence for the externally supplied voltages on VDD, IOVDD, VBAT and PVDD(for external PVDD mode). SDZ pin must be held low when supplies are not in stable operating condition. Once all the supplies are stable, SDZ pin can be asserted high for device to start operating. SDZ pin must be pulled low before any supply is ramped down below its recommended operating voltage. If using the device in external PVDD mode, the SW pad must be kept floating. Once all the supplies are valid and SDZ pin is released to high, the digital core voltage regulator powers up, and starts the internal initialization sequence. After a hardware or software reset, additional i2c commands to the device should be delayed by at-least 300us to allow the device internal blocks to be initialized. TAS2120 SLASFC6 – AUGUST 2024 www.ti.com 52 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAS2120 |
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