TAS2120 datasheet(19/63 Pages) TI

19 / 63 page

Table 6-3. SEL2 HW Mode configuration

SEL2_SCL Connection

Configuration

Direct Short to GND

I2S L or TDM0

470 to Supply

I2S R or TDM1

Direct Short to Supply

I2S (L+R)/2 or TDM2

1.2k to GND

Left-Justified L or TDM3

1.2k to Supply

Left-Justified R or TDM4

4.7k to GND

Left-Justified (L+R)/2 or TDM5

4.7k to Supply

I2S L+Tx or TDM6

24k to GND

I2S R+Tx or TDM7

24k to Supply

Reserved

Table 6-4. SEL3 HW Mode configuration

SEL3_SDA Connection

Configuration

Direct Short to GND

Data valid on rising edge

Direct Short to Supply

Data valid on falling edge

Table 6-5. SEL4 HW Mode configuration

SEL4_ADDR Connection

Configuration

Direct Short to GND

Y-bridge threshold of 80mW

Direct Short to Supply

Y-bridge threshold of 40mW

24k to Supply

Y-bridge threshold of 1mW

Table 6-6. SEL5 HW Mode configuration

SEL5_CLASSH Connection

Configuration

Direct Short to GND

1S Battery Mode, Boost ON

Direct Short to Supply

External PVDD (3S Battery)

Mode

24k to Supply

2S Battery Mode, Boost ON

6.3.1.3 Software Power Modes Control and Software Reset

The TAS2120 power state can be controlled using the register MODE[1:0]. Change in any of the MODE settings

will not cause the device to lose any of the existing device configuration register settings.

Active state: When MODE[1:0] is configured as '00', the device enters an active mode of operation with proper

power-up sequencing to minimize the click and pop.

Software shutdown state: When MODE[1:0] is configured as '10', the device enters software shutdown mode.

This mode powers down all analog blocks required to playback audio but does not cause the device to lose

before shutting down. When de-asserted, the Class-D will begin switching and volume ramp back to the

programmed digital volume setting.

Clock based Active and shutdown state: When MODE[1:0] is configured as '11' the device toggles between

Active and Shutdown state based on valid ASI clock signals applied on the ASI input pins, BCLK and FSYNC.

When clocks are applied, the device will automatically detect the clock signals and follow proper power-up

sequencing to avoid any power-up click and pop. When the audio channels are powered up and the ASI

clock is removed, the device will automatically start power-down sequencing and avoid any click and pop. It is

recommended to do a volume ramp-down in the input data stream before stopping the clocks for the best pop &

click experience (device software mute mode can be used to realize this).

www.ti.com

TAS2120

SLASFC6 – AUGUST 2024

Submit Document Feedback

Product Folder Links: TAS2120

TAS2120 Datasheet(PDF) 19 Page - Texas Instruments

TAS2120 Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL