TAS2120 datasheet(26/63 Pages) TI

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Table 6-18. Amplifier Output Level Settings

(continued)

AMP_LVL[5:0]

FULL SCALE OUTPUT

dBV

VPEAK (V)

0x04

18.993

12.6

...

0x27

1.434

1.7

0x28

0.932

1.6

0x29

0.430

1.5

0x2A

-0.071

1.4

0x2B-0x3F

Reserved

When a change in digital volume control occurs, the device ramps the volume to the new setting based on

the DVC_SLEW_RATE register bits. If DVC_SLEW_RATE is set to 0x7FFFFF, volume ramp is disabled. This

can be used to speed up start up, shutdown and digital volume changes when volume ramp is handled by the

system host. When volume ramp is disabled, the input audio data stream should be held at digital silence during

shutdown and power up of the device to avoid any clicks and pops.

The device can be put in software based mute by setting DVC_LEVEL to 0x000000 setting.

The digital voltage control registers DVC_LEVEL and DVC_SLEW_RATE registers can be configured using the

PPC3 Software Section 6.4.1.

Table 6-19. Digital Volume Control

DVC_LEVEL[23:0]

VOLUME (dB)

0x000000

Software MUTE

0x00000D (MIN)

-110

...

0x400000

0 (default)

...

0x7FB261 (MAX)

Table 6-20. Digital Volume Ramp Rate

DVC_SLEW_RATE[23:0]

RAMP RATE @ 48kHz (s)

0x00036A

1000ms

...

0x034A51

4ms (default)

...

0x7FFFFF

0 - Ramp disabled

6.4.2.2 High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers. The playback

path employs a high-pass filter (HPF) to prevent this from occurring. The HPF is a 1st order filter and can be

changed from the default 2 Hz for 48ksps fs using the AUDIO_HPF_N0, AUDIO_HPF_N1, AUDIO_HPF_D1

registers. The HPF filter frequency scales with change in the FSYNC clock and can be re-configured to achieve

the required cutoff frequency for different FSYNC clock frequencies. The coefficients can also be changed to

disable the HPF coefficients appropriately. These coefficients should be calculated and set using PPC3 Software

Section 6.4.1.

6.4.2.3 Class-D Amplifier

TAS2120

SLASFC6 – AUGUST 2024

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