TAS2120 datasheet(38/63 Pages) TI

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detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to

minimize audible artifacts.

Table 6-41. Supported SBCLK Frequencies (MHz) (48 kHz based sample rates)

Sample

Rate (kHz)

SBCLK to FSYNC Ratio

128

192

256

384

512

125

250

500

16 kHz

0.384

0.512

0.768

1.024

1.536

2.048

3.072

4.096

6.144

8.192

24 kHz

0.384

0.576

0.768

1.152

1.536

2.304

3.072

4.608

6.144

9.216

12.288

32 kHz

0.512

0.768

1.024

1.536

2.048

3.072

4.096

6.144

8.192

12.288 16.384

48 kHz

0.768

1.152

1.536

2.304

3.072

4.608

6.144

9.216

12.288 18.432 24.576

96 kHz

1.536

2.304

3.072

4.608

6.144

9.216

12.288 18.432 24.576

192 kHz

3.027

4.608

6.144

9.216

12.288 18.432 24.576

6.4.7.1 Auto clock based wakeup and clock errors

TAS2120 supports flexible operating mode transition from active to shutdown and vice-verse using ASI clock

auto detection feature. When MODE[1:0] is configured as '11' the device toggles between Active and Software

shutdown state based on valid ASI clock signals applied on the ASI input pins, ie BCLK and FSYNC. If no ASI

clocks are detected in this mode, the device remains in software shutdown, with software shutdown mode IQ

on VDD pin, until a valid BCLK and FSYNC clock is detected. Once a valid clock is detected, the device is

powered up in active state until the clocks are valid or device is shutdown using software or hardware shutdown

commands.

The device can detect and raise interrupt flags on detection of incorrect clock configurations based on status of

CLK_ERR_PWR_EN. When this bit is set high, the device monitors for activity on the clock pins and flags any

error using the latched interrupts status register. The device can also raise interrupts using IRQZ pin based on

status of the corresponding interrupt MASK registers. When the error protection bit is enabled, if a clock error is

detected, the device will automatically shutdown with proper shutdown sequencing and minimize any clicks and

pops due to invalid clocks.

When the device is in shutdown state, the clock error detection can be delayed to provide system with time

required to settle the input clocks. This power up delay in clock error detection is controlled using an internal

pre-power up clock error detection timer configured by CLK_HALT_TIMER. If device doesn't detect a valid clock

at the end of the CLK_HALT_TIMER expiry, the Pre-Power-up Clock error is flagged on INT_LTCH4[2] bit, and

corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK4[2] bit. When MODE[1:0]

is configured as '11' (Wake-up on ASI mode), CLK_HALT_TIMER of '000' is not recommended and it stops the

device from entering the software shutdown and increases the VDD IQ while the device is shutdown.

Once the device is powered up, the external and internally generated clocks are constantly monitored based on

status of CLK_ERR_PWR_EN bit. If enabled, any error in external or internal clock is flagged using the clock

error status register INT_LTCH2[3] bit, and corresponding interrupt can be generated on IRQZ pin based on

status of INT_MASK2[3].

For system flexibility, the device will also set the error status for the type of detected clock error. The device

can also be configured to raise an interrupt on IRQZ pin for any specific type of clock error, instead of using

the generic clock error interrupt generation. Table 6-44 below explains the different type of clock errors and

corresponding status bits and interrupt MASK register bits. One or more register bits in the table below can be

set based on the type of clock error detected.

If the device shuts down due to any type of clock error, it can attempt to re-power itself automatically when

MODE[1:0] is set to '11'.

Table 6-42. Clock Error detection control

CLK_ERR_PWR_EN

Setting

Disabled

TAS2120

SLASFC6 – AUGUST 2024

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