PM7346 datasheet(23/419 Pages) PMC

23 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 2

• Implements the ATM physical layer for Broadband ISDN according to ITU-T

Recommendation I.432.

• Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.

• Can be configured to be used solely as a DS3, E3, or J2 Framer.

• When configured to operate as a DS3, E3, or J2 Framer, gapped transmit and

receive clocks can be optionally generated for interface to devices which only

need access to payload data bits.

• Provides support for an arbitrary rate external transmission system interface

up to a maximum rate of 52 Mbit/s which enables the S/UNI-QJET to be used

as a quad ATM cell delineator.

• Uses the PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, and

PM6344 EQUAD T1 and E1 framer/line interface chips for DS1 and E1

applications.

• Provides programmable pseudo-random test pattern generation, detection,

and analysis features.

• Provides integral transmit and receive HDLC controllers with 128-byte FIFO

depths.

• Provides performance monitoring counters suitable for accumulation periods

of up to 1 second.

• Provides an 8-bit microprocessor interface for configuration, control and

status monitoring.

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

• Low power 3.3V CMOS technology with 5V tolerant inputs.

• Available in a high density 256-pin SBGA package (27mm x 27mm).

The receiver section:

• Provides frame synchronization for the M23 or C-bit parity DS3 applications,

alarm detection, and accumulates line code violations, framing errors, parity

errors, path parity errors and FEBE events. In addition, far end alarm channel

PM7346 Datasheet(PDF) 23 Page - PMC-Sierra, Inc