PM7346 datasheet(93/419 Pages) PMC

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PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 72

of RFCLK). The RCA (and DRCA[x]) status changes from available to

unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty

(RCALEVEL0 is logic 0). This interface also indicates FIFO overruns via a

maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is

a logic 0 will output invalid data.

9.11 CPPM Cell and PLCP Performance Monitor

The Cell and PLCP Performance Monitor (CPPM) Block interfaces directly to the

SPLR to accumulate bit interleaved parity error events, framing octet error

events, and far end block error events in saturating counters. When the PLCP

framer (SPLR) declares loss of frame, bit interleaved parity error events, framing

octet error events, far end block error events, header check sequence error

events are not counted.

When an accumulation interval is signaled by a write to the CPPM register

address space or to the S/UNI-QJET Identification, Master Reset, and Global

Monitor Update register, the CPPM transfers the current counter values into

holding registers and resets the counters to begin accumulating error events for

the next interval. The counters are reset in such a manner that error events

occurring during the reset period are not missed.

9.12 PRGD Pseudo-Random Sequence Generator/Detector

The Pseudo-Random Sequence Generator/Detector (PRGD) block is a software

programmable test pattern generator, receiver, and analyzer. Two types of test

patterns (pseudo-random and repetitive) conform to ITU-T O.151.

The PRGD can be programmed to generate any pseudo-random pattern with

length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in

length. In addition, the PRGD can insert single bit errors or a bit error rate

between 10-1 to 10-7.

The PRGD can be programmed to check for the presence of the generated

pseudo-random pattern. The PRGD can perform an auto-synchronization to the

expected pattern, and generate interrupts on detection and loss of the specified

pattern. The PRGD can accumulate the total number of bits received and the

total number of bit errors in two saturating 32-bit counters. The counters

accumulate over an interval defined by writes to the S/UNI-QJET

Identification/Master Reset, and Global Monitor Update register (register 006H)

or by writes to any PRGD accumulation register. When an accumulation is forced

by either method, then the holding registers are updated, and the counters reset

to begin accumulating for the next interval. The counters are reset in such a way

PM7346 Datasheet(PDF) 93 Page - PMC-Sierra, Inc

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