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PM7346 Datasheet(PDF) 76 Page - PMC-Sierra, Inc

Part # PM7346
Description  SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PDF  419 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7346 Datasheet(HTML) 76 Page - PMC-Sierra, Inc

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PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 55
Pin Name
Type
Pin No.
Function
VSS[30]
VSS[31]
VSS[32]
Ground
Y18
Y19
Y20
DC Ground. The DC Ground pins should
be connected to GND.
Notes on Pin Description:
1. All S/UNI-QJET inputs and bi-directionals present minimum capacitive
loading and operate at TTL logic levels.
2. All S/UNI-QJET outputs and bi-directionals have at least 3 mA drive
capability. The data bus outputs, D[7:0], have 3 mA drive capability. The
FIFO interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA,
and DTCA[4:1], have 12 mA drive capability. The outputs TCLK[4:1],
TPOS/TDATO[4:1], TNEG/TOHM[4:1],
TPOHFP/TFPO/TMFPO/TGAPCLK[4:1], LCD/RDATO[4:1],
RPOH/ROVRHD[4:1], RPOHCLK/RSCLK/RGAPCLK[4:1], and
REF8KO/RPOHFP/RFPO/RMFPO[4:1] have 6 mA drive capability. All other
outputs have 3 mA drive capability.
3. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
4. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK[4:1], and
RCLK[4:1] are schmitt trigger input pads.
5. RFCLK and TFCLK are 3.3 V only input pins – they are not 5 V tolerant.
Connecting a 5 V signal to these inputs may result in damage to the part.
6. The VSS [32:1] ground pins are not internally connected together. Failure to
connect these pins externally may cause malfunction or damage the
S/UNI-QJET.
7. The VDD[28:1] power pins are not internally connected together. Failure to
connect these pins externally may cause malfunction or damage the device.
These power supply connections must all be utilized and must all connect to
a common +3.3 V or ground rail, as appropriate.
8. During power-up and power-down, the voltage on the BIAS pin must be kept
equal to or greater than the voltage on the VDD [28:1] pins, to avoid damage
to the device.



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