PM7346 datasheet(86/419 Pages) PMC

86 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 65

will never declare Loss of Frame or search for a new frame alignment due to

excess framing bit errors.

J2 extended Loss of Frame detection is provided as recommended by ITU-T

G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While

integrating up to assert LOF, the counter will integrate up when the framer

asserts an Out of Frame condition and integrates down when the framer de-

asserts the Out of Frame condition. Once an LOF is asserted, the framer must

not assert OOF for the entire integration period before LOF is de-asserted.

9.4

PMON Performance Monitor Accumulator

The Performance Monitor (PMON) Block interfaces directly with either the DS3

Framer (T3-FRMR) to accumulate line code violation (LCV) events, parity error

(PERR) events, path parity error (CPERR) events, far end block error (FEBE)

events, excess zeros (EXZS), and framing bit error (FERR) events using

saturating counters; the E3 Framer (E3-FRMR) to accumulate LCV, PERR (in

G.832 mode), FEBE and FERR events; or the J2 Framer (J2-FRMR) to

accumulate LCVs, CRC errors (in the PERR counter), Framing bit errors (FERR),

and excess zeros (EXZS). The PMON stops accumulating error signal from the

E3, DS3, or J2 Framers once frame synchronization is lost.

When an accumulation interval is signaled by a write to the PMON register

address space or a write to the S/UNI-QJET Identification, Master Reset, and

Global Monitor Update register, the PMON transfers the current counter values

into microprocessor accessible holding registers and resets the counters to begin

accumulating error events for the next interval. The counters are reset in such a

manner that error events occurring during the reset period are not missed.

When counter data is transferred into the holding registers, an interrupt is

generated, providing the interrupt is enabled. If the holding registers have not

been read since the last interrupt, an overrun status bit is set. In addition, a

accumulation interval.

9.5

RBOC Bit-Oriented Code Detector

The Bit-Oriented Code Detector is only used in DS3 C-bit Parity or J2 mode.

The Bit-Oriented Code Detector (RBOC) Block detects the presence of 63 of the

64 possible bit-oriented codes (BOCs) contained in the DS3 C-bit parity far-end

alarm and control (FEAC) channel or in the J2 datalink signal stream. The 64th

code ("111111") is similar to the HDLC flag sequence and is ignored.

PM7346 Datasheet(PDF) 86 Page - PMC-Sierra, Inc

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