PM7346 datasheet(92/419 Pages) PMC

92 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 71

Figure 11

- HCS Verification State Diagram

DE TE CTIO N

MO D E

AT M DELINEATIO N

SYNC S T AT E

CO R R E C TIO N

MO D E

N o E rro rs D e te cte d in M

(M = 1, 2 , 4, or 8) con se cutiv e ce lls

(P ass Last C ell)

A pp aren t M ulti-B it E rror

(D rop C e ll)

N o E rro rs

Dete cte d

(P ass C ell)

A LPHA

co ns ec utiv e

inco rre ct H C S 's

(T o HU NT state)

DE LT A

co ns ec utiv e

correct H C S's

(Fro m P R E S Y N C

state)

S ingle B it E rro r

(C orrect error

and pa ss cell)

D rop C e ll

9.10 RXFF Receive FIFO

The Receive FIFO (RXFF) provides FIFO management and the S/UNI-QJET

receive cell interface. The receive FIFO contains four cells. The FIFO provides

the cell rate decoupling function between the transmission system physical layer

and the ATM layer.

In general, the management functions include filling the receive FIFO, indicating

when the receive FIFO contains cells, maintaining the receive FIFO read and

write pointers, and detecting FIFO overrun and underrun conditions.

The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock

(RFCLK) and read enable signal (RENB). The receive FIFO output bus

(RDAT[15:0]) is tri-stated when RENB is logic 1 or if the PHY device address

(RADR[4:0]) selected does not match this device's address. The interface

indicates the start of a cell (RSOC) and the receive cell available status (RCA

and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges

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