PM7346 datasheet(57/419 Pages) PMC

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PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 36

Pin Name

Type

Pin No.

Function

ROHCLK[4]

ROHCLK[3]

ROHCLK[2]

ROHCLK[1]

Output

Receive DS3/E3/J2 Overhead Clock

(ROHCLK[4:1]). ROHCLK[4:1] is active

when a DS3, E3, or J2 stream is being

processed. ROHCLK[4:1] is nominally a

526 kHz clock when processing DS3, a

1.072 MHz clock when processing G.832

E3, a 1.074 MHz clock when processing

G.751 E3, and a gapped 6.312 MHz clock

with an average frequency of 168 kHz for

J2. ROH[4:1], and ROHFP[4:1] are

updated on the falling edge of

ROHCLK[4:1].

REF8KO[4]

REF8KO[3]

REF8KO[2]

REF8KO[1]

Output

U12

Reference 8kHz Output (REF8KO[4:1]).

REF8KO[4:1] is an 8kHz reference derived

from the receive clocks on RCLK[4:1]. A

free-running divide-down counter is used

to generate REF8KO[4:1] so it will not

glitch on reframe actions. REF8KO[4:1]

will pulse high for approximately 1

RCLK[4:1] cycle every 125 µs.

REF8KO[4:1] should be treated as a

glitch-free asynchronous signal.

RPOHFP[4]

RPOHFP[3]

RPOHFP[2]

RPOHFP[1]

Receive PLCP Overhead Frame Position

(RPOHFP[4:1]). RPOHFP[4:1] locates the

individual PLCP path overhead bits in the

receive overhead data stream, RPOH[4:1].

RPOHFP[4:1] is logic 1 while bit 1 (the

most significant bit) of the path user

channel octet (F1) is present in the

RPOH[4:1] stream. RPOHFP[4:1] is

updated on the falling edge of

RPOHCLK[4:1]. RPOHFP[4:1] is available

when the PLCPEN register bit is logic 1 in

the SPLR Configuration Register.

PM7346 Datasheet(PDF) 57 Page - PMC-Sierra, Inc

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