TMPR3916 datasheet(114/225 Pages) TOSHIBA

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Chapter 6 Direct Memory Access Controller (DMAC)

Preliminary

6-1

Direct Memory Access Controller (DMAC)

The purpose of the Direct Memory Access Controller (DMAC) is to accelerate system speed and to make it

easier for software to transfer data between memory and peripheral devices. The DMA Controller contains the

following features:

•

The DMAC consists of two independent channels: channel 0 and channel 1. Channel 0 has higher priority

than channel 1 on GBUS transfers.

•

DMA transactions are only possible from device to memory or from memory to device. Devices are for

example UART and TXSEI.

•

The DMA transfer will start after request of a peripheral device. That’s why only data transfer will happen,

when the device needs data. The UARTs, the TXSEI or an external device can send a request.

•

At the end of a transaction or at the occurrence of an error an interrupt will be caused. The interrupt is only

maskable in the Interrupt Controller (INTC).

The following sequence shows the principle use of the DMA Controller to transfer data between memory and

a peripheral device:

Configure the DMA and the peripheral device. Set the number of Bytes to be transferred.

The DMA Controller waits for a request of the peripheral device.

The DMA Controller transfers data between memory and the peripheral device.

The DMA Controller sends an acknowledge to the peripheral device.

If there are more bytes left to transfer go to point 2.

The DMA Controller causes an interrupt.

TMPR3916 Datasheet(PDF) 114 Page - Toshiba Semiconductor