TMPR3916 datasheet(118/225 Pages) TOSHIBA

118 / 225 page

Chapter 6 Direct Memory Access Controller (DMAC)

Preliminary

6-5

6.2

Registers

Overview:

(short name)

Physical

Address (hex)

Name

Function

ODR0

ODR1

1C060000

1C060010

Operation Definition Register

Basic channel settings

CCR0

CCR1

1C060001

1C060011

Channel Control Register

Controls channel operations

CER0

CER1

1C060002

1C060012

Channel Error Register

Cause of an error or interrupt

CSR0

CSR1

1C060003

1C060013

Channel Status Resister

Channel operating status

SAR0

SAR1

1C060004

1C060014

Source Address Register

Specifies the address, where to

get data from

DAR0

DAR1

1C060008

1C060018

Destination Address Register

Specifies the address, where to

write data to

BCR0

BCR1

1C06000C

1C06001C

Byte Count Register

Specifies the number of transfer

data in byte units

Operation Definition Register (ODR)

Bit

3130

292827

262524

Name

SAC

DAC

PSIZ

OSIZ

MSIZ

BST

Bit

Name

Function

Reset

Value

R/W

SAC

Specifies, if the Source Address Register should count up.

0 = Source address does not count up (device to memory transfer)

1 = Source address counts up on each transfer

(memory to device transfer)

This bit should be set to 0, when the DAC bit is set to 1.

R/W

DAC

Specifies, if the Destination Address Register should count up.

0 = Destination address does not count up

(memory to device transfer)

1 = Source address counts up on each transfer

(device to memory transfer)

This bit should be set to 0, when the SAC bit is set to 1.

R/W

29:28

PSIZ

Specifies the size of the device data register.

00 = 8 bits, register bits [31:24]

01 = 16 bits, register bits [31:16]

10 = 32 bits, register bits [31:0]

11 = Setting prohibited

R/W

27:26

OSIZ

Specifies the width of DMA transfer.

00 = 8 bits

01 = 16 bits

10 = 32 bits

11 = Setting prohibited

R/W

MSIZ

Specifies the bus width of the memory.

0 = 32 bits

1 = 16 bits (there is no use for this setting)

R/W

BST

Specifies the detection mode for the request signal from the device.

0 = Edge detection

1 = Level detection

For UART and TXSEI request signals use level detection.

R/W

TMPR3916 Datasheet(PDF) 118 Page - Toshiba Semiconductor

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