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TMPR3916 Datasheet(PDF) 119 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 119 Page - Toshiba Semiconductor

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Chapter 6 Direct Memory Access Controller (DMAC)
Preliminary
6-6
Channel Control Register (CCR)
Bit
2322
212019
181716
Name
RST
ABT
CEN
RPL

ETE
Bit
Name
Function
Reset
Value
R/W
23
RST
Performs a software reset on all of the channel registers.
0 = Normal operation
1 = Executes software reset
0
R/W
22
ABT
Termination of channel operations regardless of the operating
status.
0 = Normal operation
1 = Termination of current DMA transaction
0
R/W
21
Wired to zero.
0R/W
20
CEN
Sets the channel to operating mode.
0 = Channel is inactive
1 = Start DMA transaction
0
R/W
19
RPL
Specifies the polarity of the device request signal.
0 = Negative logic (low level / falling edge)
1 = Positive logic (high level / rising edge)
UART and TXSEI use negative logic.
0
R/W
18:17
Wired to zero
00
R
16
ETE
Decides if the request signal from a device is provided to the DMAC.
0 = No request signal is provided to the DMAC
1 = Request signal is provided to the DMAC
Without setting this bit to 1, the DMA controller does not start a
transaction.
0
R/W
Channel Error Register (CER)
Bit
1514
131211
10
9
8
Name
SWA
BER
ACE
CONF
SBE
DBE
BCE
AER
Bit
Name
Function
Reset
Value
R/W
15
SWA
Software Abort:
If this bit is set to 1, the software has terminated the current DMA
transaction
0
R
14
BER
Bus Error:
If this bit is set to 1, a bus error has occurred on DMA transfer.
0
R
13
ACE
Address or Count Error: (ACE = BCE + AER)
If this bit is set to 1, a byte count error (BCE, bit 9) or an address
boundary error (AER, bit 8) has occurred.
0
R
12
CONF
Configuration Error:
If this bit is set to 1, the software has made invalid settings in the
Operation Definition Register (ODR) or in the Channel Control
Register (CCR).
0
R
11
SBE
Bus Error on Source Address Access:
If this bit is set to 1, a bus error has occurred during read from a
source.
0
R
10
DBE
Bus Error on Destination Address Access:
If this bit is set to 1, a bus error has occurred during write to a
destination.
0
R



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