ADPL74101 datasheet(28/49 Pages) AD

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Data Sheet

ADPL74101

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A PLL is also available on the ADPL74101 to synchronize the internal oscillator to an external clock source connected

to the PLLIN/ SPREAD pin. After the PLL locks, TG is synchronized to the rising edge of the external clock signal. See

the Phase-Locked Loop and Frequency Synchronization section for more details.

Selecting the Light-Load Operating Mode

The ADPL74101 can be set to enter high-efficiency Burst Mode operation, constant-frequency pulse skipping mode,

or forced continuous conduction mode at light load currents. To select Burst Mode operation, tie the MODE pin to

GND. To select forced continuous operation, tie the MODE pin to INTVCC. To select pulse skipping mode, tie the MODE

pin to INTVCC through a 100kΩ resistor. An internal 100kΩ resistor from the MODE pin to GND selects Burst Mode if

the pin is floating. When synchronized to an external clock via the PLLIN/SPREAD pin, the ADPL74101 operates in

pulse-skipping mode when selected. Otherwise, the ADPL74101 operates in forced continuous mode.

Table 5 summarizes the use of the MODE pin to select the light load operating mode.

Table 5. Using the MODE Pin to Select Light Load Operating Mode

MODE PIN

LIGHT-LOAD OPERATING MODE

MODE WHEN SYNCHRONIZED

0V or Floating

Burst Mode

Forced Continuous

100kΩ to INTVCC

Pulse-Skipping

INTVCC

Forced Continuous

The requirements of each application dictate the appropriate choice for the light-load operating mode. In Burst Mode

operation, the inductor current is not allowed to reverse. The reverse current comparator turns off the bottom FET

before the inductor current reaches zero, preventing it from reversing and going negative. Therefore, the regulator

operates in discontinuous operation. In addition, when the load current is light, the inductor current begins bursting

at frequencies lower than the switching frequency and enters a low current sleep mode when not switching. As a

result, Burst Mode operation has the highest possible efficiency at light loads.

In forced continuous mode, the inductor current is allowed to reverse at light loads and switches at the same

frequency regardless of the load. In this mode, the efficiency at light loads is considerably lower than in Burst Mode

operation. However, continuous operation has the advantage of lower output-voltage ripple and less interference to

audio circuitry. In forced continuous mode, the output ripple is independent of the load current.

In pulse-skipping mode, constant-frequency operation is maintained down to approximately 1% of the designed

maximum output current. At very light loads, the PWM comparator can remain tripped for several cycles and force

the top FET to remain off for the same number of cycles (skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple, low

audio noise, and reduced RF interference compared to Burst Mode operation. Pulse skipping mode provides higher

light-load efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Consequently,

pulse-skipping mode represents a compromise between light-load efficiency, output ripple, and EMI.

In some applications, it may be desirable to change the light load operating mode based on the conditions present

in the system. For example, if a system is inactive, the user can select high-efficiency Burst Mode operation by keeping

the MODE pin set to 0V. When the system wakes, the user can send an external clock to PLLIN/ SPREAD, or tie MODE

to INTVCC to switch to low noise forced continuous mode. These on-the-fly mode changes can allow an individual

application to benefit from the advantages of each light load operating mode.

ADPL74101 Datasheet(PDF) 28 Page - Analog Devices

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