ADPL74101 datasheet(36/49 Pages) AD

36 / 49 page

Data Sheet

ADPL74101

analog.com

Rev. 0

36 of 49

Fault Conditions: Current Limit and Foldback

The ADPL74101 includes current foldback to reduce the load current when the output is shorted to GND. If the output

voltage falls below 70% of its regulation point, the maximum sense voltage is progressively lowered from 100% to

40% of its maximum value. Under short-circuit conditions with low duty cycles, the ADPL74101 begins cycle skipping

to limit the short-circuit current. In this situation, the bottom FET dissipates most of the power, but less than in

normal operation. The short-circuit ripple current (ΔIL(SC)) is determined by tON(MIN) ≈ 40ns, the input voltage, and the

inductor value given by Equation 23, as follows:

∆IL = tON(MIN) ×

��

(23)

The resulting average short-circuit current (ISC) is given by Equation 24, as follows:

ISC = 40% × ILIM(MAX) −

∆IL(SC)

(24)

where ILIM(MAX) is the maximum peak inductor current.

Fault Conditions: Overvoltage Protection

If the output voltage rises 10% above the set regulation point, the top FET turns off, and the inductor current is not

allowed to reverse until the overvoltage condition clears.

Fault Conditions: Overtemperature Protection

At higher temperatures or when the internal power dissipation causes excessive self-heating (for example: a short

from INTVCC to GND), the internal overtemperature shutdown circuitry shuts down the ADPL74101. When the internal

die temperature exceeds 180°C, the INTVCC LDO regulator and gate drivers disable. When the die cools to 160°C, the

ADPL74101 enables the INTVCC LDO regulator and resumes operation, starting with a soft-start startup. Avoid long-

term overstress (TJ > 125°C) because it can degrade the device performance or shorten the device life.

Phase-Locked Loop and Frequency Synchronization

The ADPL74101 has an internal PLL that allows the turn-on of the top FET to be synchronized to the rising edge of an

external clock signal applied to the PLLIN/SPREAD pin.

Rapid phase locking can be achieved by using the FREQ pin to set a free-running frequency near the desired

synchronization frequency. Before synchronization, the PLL is prebiased to the frequency set by the FREQ pin.

Consequently, the PLL only needs to make minor adjustments to achieve phase lock and synchronization. Although

it is not required, placing the free-running frequency near the external clock frequency prevents the oscillator from

passing through a large range of frequencies as the PLL locks.

When synchronized to an external clock, the ADPL74101 operates in pulse-skipping mode when the MODE pin is

selected, or in forced continuous mode otherwise. The ADPL74101 is guaranteed to synchronize to an external clock

applied to the PLLIN/SPREAD pin that swings up to at least 2.2V and down to 0.5V or less. Note that the ADPL74101

can only be synchronized to an external clock frequency between 100kHz to 1MHz.

ADPL74101 Datasheet(PDF) 36 Page - Analog Devices