ADPL74101 datasheet(21/49 Pages) AD

21 / 49 page

Data Sheet

ADPL74101

analog.com

Rev. 0

21 of 49

In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this

mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the

advantage of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the

output ripple is independent of the load current.

When the MODE pin is connected for pulse skipping mode, the ADPL74101 operates in pulse-width modulation (PWM)

pulse skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately

1% of the designed maximum output current. At light loads, ICMP can remain tripped for several cycles and force the

top FET to stay off for the same number of cycles (that is, skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as

low audio noise and reduced RF interference, as compared to Burst Mode operation. Pulse skipping mode provides

higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation.

Unlike forced continuous mode and pulse-skipping mode, Burst Mode operation cannot be synchronized to an

external clock. Therefore, if Burst Mode operation is selected and the switching frequency is synchronized to an

external clock applied to the PLLIN/SPREAD pin, the ADPL74101 switches from Burst Mode operation to forced

continuous mode.

Frequency Selection, Spread Spectrum, and Phase-Locked Loop

(FREQ and PLLIN/SPREAD Pins)

The free-running switching frequency of the ADPL74101 controller is selected using the FREQ pin. Tying FREQ to GND

selects 370 kHz. Placing a resistor between FREQ and GND allows the frequency to be programmed between 100kHz

and 1MHz.

Switching regulators can be particularly troublesome for applications where electromagnetic interference (EMI) is a

concern. To improve EMI, the ADPL74101 can operate in spread spectrum mode, which is enabled by tying the

PLLIN/SPREAD pin to INTVCC. This feature varies the switching frequency within the typical boundaries of the

frequency set by the FREQ pin, and +20%.

A phase-locked loop (PLL) is available on the ADPL74101 to synchronize the internal oscillator to an external clock

source connected to the PLLIN/SPREAD pin. The PLL of the ADPL74101 aligns the turn-on of the external top FET to

the rising edge of the synchronizing signal.

The PLL frequency is prebiased to the free-running frequency set by the FREQ pin before the external clock is applied.

If prebiased near the external clock frequency, the PLL only needs to make slight changes to synchronize the rising

edge of the external clock to the rising edge of TG. For faster lock-in to the external clock, use the FREQ pin to set the

internal oscillator to approximately the external clock's frequency. The PLL of the ADPL74101 is guaranteed to lock

to an external clock source with a frequency between 100kHz and 1MHz.

The PLLIN/SPREAD pin is transistor-transistor logic (TTL)-compatible with thresholds of 1.6V (rising) and 1.1V

(falling), and is guaranteed to operate with a clock signal swing of 0.5V to 2.2V.

ADPL74101 Datasheet(PDF) 21 Page - Analog Devices