ADPL74101 datasheet(29/49 Pages) AD

29 / 49 page

Data Sheet

ADPL74101

analog.com

Rev. 0

29 of 49

Dead Time Control

The ADPL74101 uses dead time control. The dead time is measured between one FET turning off and the other FET

turning on. The delay between BG and TG transitions is fixed to approximately 20 ns.

Figure 33. Dead Time Control

Power FET Selection

Two external power FETs must be selected for the ADPL74101: one N-channel FET for the top (main) switch and one

N-channel FET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC

regulation point (4V to 5.5V). For silicon MOSFETs, logic-level threshold MOSFETs are required in most applications.

Pay close attention to the breakdown voltage (BVDSS) specification for the FETs as well.

Selection criteria for the power FETs include the on resistance (RDS(ON)), Miller capacitance (CMILLER), input voltage, and

maximum output current. CMILLER can be approximated from the gate-charge curve typically provided in the

data sheet of the FET manufacturer. CMILLER is equal to the increase in gate charge along the horizontal axis while the

curve is approximately flat, divided by the specified change in the voltage difference between the drain and source

terminals of the MOSFET (VDS). This result is then multiplied by the ratio of the application applied VDS to the gate-

charge-curve specified VDS. When the device is operating in continuous mode, the duty cycles for the top and bottom

FETs are given by Equation 10 and Equation 11, as follows:

Main Switch Duty Cycle =

VOUT

VIN

(10)

Synchronous Switch Duty Cycle =

VIN−VOUT

VIN

(11)

The FET power dissipation at maximum output current is given by Equation 12 and Equation 13, as follows:

PMAIN =

VOUT

VIN

(IMAX)2 × (1 + δ)RDS(ON) + (VIN)2(

IMAX

)

× (R

DR)(CMILLER) ×

(

VINTVCC−VTHMIN

VTHMIN

)(f)

(12)

PSYNC =

VIN−VOUT

VIN

(IMAX)2(1 + δ)RDS(ON)

(13)

where:

PMAIN is the power dissipation from the main switch.

δ is the temperature dependency of RDS(ON) (δ ≈ 0.005/°C).

RDR is the effective driver resistance at the FET’s Miller threshold voltage (RDR ≈ 2Ω).

VINTVCC is the INTVCC voltage.

VTHMIN is the typical FET minimum threshold voltage.

PSYNC is the power dissipation from the synchronous switch.

TG MINUS SW

GND

VIN

20ns

ADPL74101 Datasheet(PDF) 29 Page - Analog Devices

ADPL74101 Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL