ADPL74101 datasheet(35/49 Pages) AD

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Data Sheet

ADPL74101

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Rev. 0

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However, for 3.3V and other low-voltage outputs, additional circuitry is required to derive INTVCC power from the

output.

The following list summarizes the three possible connections for EXTVCC:

1. EXTVCC grounded. This connection causes the internal VIN LDO regulator to power INTVCC, resulting in an

efficiency penalty of up to 10% or more at high input voltages.

2. EXTVCC is connected directly to the regulator output. This connection is the normal connection for an

application with an output range of 5V to 30V and provides the highest efficiency.

3. EXTVCC connected to an external supply. If an external supply is available, it can be used to power EXTVCC,

provided that it is compatible with the FET gate drive requirements. This supply can be higher or lower than

VIN. However, a lower EXTVCC voltage results in higher efficiency.

4. EXTVCC connected to an output-derived boost or charge pump. For regulators with outputs below 5V,

efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that is boosted above

the EXTVCCswitchover threshold.

Topside FET Driver Supply (C

An external bootstrap capacitor (CB) connected to the BOOST pin supplies the gate drive voltage for the topside FET.

CB in Figure 28 (Functional Diagram) is charged via an internal switch from DRVCC when the SW pin is low, and the

bottom FET is turned on. The on-resistance of the internal switch is approximately 7Ω. To deliver more charge current

to CB under certain operating conditions, place an external Schottky diode between BSTVCC and BOOST to bypass

most of the internal switch resistance between DRVCC and BOOST.

When the topside FET turns on, the driver places the CB voltage across the gate source of the desired FET, which

enhances the FET and turns on the topside switch. The switch node voltage, SW, rises to VIN, and the BOOST pin

follows. With the topside FET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of CB

must be 100 times the total input capacitance of the topside FETs. For a typical application, a value of CB = 0.1μF is

sufficient.

Minimum On-Time Considerations

The minimum on time (tON(MIN)) is the smallest time duration that the ADPL74101 is capable of turning on the top FET.

tON(MIN) is determined by internal timing delays and the gate charge required to turn on the FET. Low-duty-cycle

applications can approach this minimum on time limit. Take care to ensure the results in Equation 22, as follows:

tON(MIN) <

VOUT

VIN× f

(22)

If the duty cycle falls below the minimum on-time requirement, the controller begins to skip cycles. The output

voltage continues to be regulated, but the ripple voltage and current increases. The minimum on-time for the

ADPL74101 is approximately 40ns. However, as the peak sense voltage decreases, the minimum on time gradually

increases to about 60ns. This change is of particular concern in forced continuous applications with low ripple

current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, significant cycle

skipping can occur with correspondingly larger current and voltage ripple.

ADPL74101 Datasheet(PDF) 35 Page - Analog Devices

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