ADPL74101 datasheet(30/49 Pages) AD

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Data Sheet

ADPL74101

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Rev. 0

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Both FETs have I2R losses (I2R is the power loss equation of the FETs), whereas the main N-channel equations include

an additional term for transition losses, which are highest at high input voltages. For VIN < 20 V, the high-current

efficiency generally improves with larger FETs. However, for VIN > 20 V, the transition losses rapidly increase, so that

using a higher RDS(ON) device with lower CMILLER provides higher efficiency. The synchronous FET losses are greatest at

high input voltage when the top switch duty factor is low, or during a short circuit when the synchronous switch is

on close to 100% of the period.

CIN and COUT Selection

The selection of the input capacitance (CIN) is usually based on the worst-case rms current drawn through the input

network (battery, fuse, or capacitor). The highest VOUT × IOUT product needs to be used in Equation 14 to determine

the maximum rms capacitor current requirement.

In continuous mode, the source current of the top FET is a square wave with a duty cycle of VOUT/VIN. To prevent large

voltage transients, use a low effective series resistance (ESR) capacitor sized for the maximum rms current (IRMS). At

IMAX, the maximum rms capacitor current is given by Equation 14, as follows:

CIN Required IRMS

≈

IMAX

VIN

((VOUT)(VIN − VOUT))1/2

(14)

Equation 14 has a maximum at VIN = 2 VOUT, where IRMS = IOUT/2 (IOUT is the output current). This simple worst-case

condition is commonly used for design because even significant deviations do not offer much relief. Note that the

ripple current ratings of capacitor manufacturers are often based on only 2000 hours of life. This basis makes it

advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required.

Several capacitors can be paralleled to meet size or height requirements in the design. Due to the high operating

frequency of the ADPL74101, ceramic capacitors can also be used for CIN. Consult the manufacturer if there are any

questions.

Placing a small (0.1μF to 1μF) bypass capacitor between the ADPL74101 VIN pin and GND, close to the ADPL74101, is

also recommended. An optional 1Ω to 10Ω resistor placed between CIN and the VIN pin provides further isolation from

a noisy input supply.

The selection of the output capacitance (COUT) is driven by the ESR. Typically, once the ESR requirement is satisfied,

the capacitance is adequate for filtering. The output ripple (ΔVOUT) is approximated by Equation 15, as follows:

∆�� ≈ ∆��(�� +

8��

)

(15)

where:

f is the operating frequency.

∆

IL is the ripple current in the inductor.

The output ripple is highest at the maximum input voltage because ΔIL increases with the input voltage.

ADPL74101 Datasheet(PDF) 30 Page - Analog Devices

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