ADPL74101 datasheet(39/49 Pages) AD

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Data Sheet

ADPL74101

analog.com

Rev. 0

39 of 49

Design Example

As a design example, assume the nominal input voltage (VIN(NOMINAL)) = 12V, VIN(MAX) = 22V, VOUT = 3.3V, IOUT = 20A, and

fSW = 1MHz.

Use the following steps to design an application circuit:

Set the operating frequency. The frequency is not one of the internal preset values. Therefore, a resistor

from the FREQ pin to GND is required, with a value given by Equation 27, as follows:

RFREQ(in kΩ) =

37MHz

1MHz

= 37kΩ

(27)

Determine the inductor value. Initially, select a value based on an inductor ripple current of 30%. To

calculate the inductor value, use Equation 28, as follows:

L =

VOUT

fSW× ∆IL

(1 −

VOUT

VIN(NOMINAL)

) = 0.4µH

(28)

The highest value of the ripple current occurs at the maximum input voltage. In this case, the ripple at VIN =

22V is 35%.

Verify that the minimum on-time of 40ns is not violated. The minimum on-time occurs at VIN(MAX), as shown

in Equation 29:

tON(MIN) =

VOUT

VIN(MAX)× fSW

= 150ns

(29)

This time is sufficient to satisfy the minimum on-time requirement. If the minimum on-time is violated, the

ADPL74101 skips pulses at high input voltage, resulting in lower frequency operation and higher inductor

current ripple than desired. If undesirable, this behavior can be avoided by decreasing the frequency (with

the inductor value adjusted accordingly) to avoid operation near the minimum on time.

Select the RSENSE resistor value. The peak inductor current is the maximum DC output current plus half of the

inductor ripple current, or 20A × (1 + 0.30/2) = 23A in this case. The RSENSEresistor value can then be calculated

based on the minimum value for the maximum current sense threshold (45mV for ILIM = float), given by

Equation 30, as follows:

RSENSE ≤

45mV

23A

≅ 2

mΩ

(30)

To allow for additional margin, a lower value RSENSE can be used (for example, 1.8mΩ). However, ensure that

the inductor saturation current has sufficient margin above VSENSE(MAX)/RSENSE, where the maximum value of

55mV is used for VSENSE(MAX).

Select the feedback resistors. If light-load efficiency is required, high-value feedback resistors can be used

to minimize the current due to the feedback divider. However, in most applications, a feedback divider

current in the range of 10μA to 100μA or more is acceptable. For a 50μA feedback divider current, RA =

0.8V/50μA = 16kΩ. RB can then be calculated as RB = RA(3.3V/0.8V – 1) = 50kΩ.

Select the FETs. The best way to evaluate FET performance in a particular application is to build and test

the circuit on the bench, facilitated by an ADPL74101 evaluation board. However, an educated guess

about the application is helpful to initially select FETs. Because this is a high-current, low-voltage

application, I2R losses are likely to dominate over transition losses for the top FET. Therefore, choose a

FET with lower RDS(ON) rather than lower gate charge to minimize the combined loss terms. The bottom

FET does not experience transition losses, and its power loss is generally dominated by I2R losses. For this

reason, the bottom FET is typically chosen to be of lower RDS(ON) and higher gate charge than the top FET.

ADPL74101 Datasheet(PDF) 39 Page - Analog Devices

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