ADPL74101 datasheet(12/49 Pages) AD

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Data Sheet

ADPL74101

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Rev. 0

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VPRG

Output Voltage Control Pin. VPRG sets the adjustable output mode using external

feedback resistors or the fixed 12V or 5V output mode. Floating VPRG programs the

output from 0.8V to 60V with an external resistor divider, regulating VFB to 0.8V.

Connect VPRG to INTVCC or GND to program the output to 12V or 5V, respectively,

through an internal resistor divider on VFB.

VIN

Main Supply Pin. A bypass capacitor must be tied between VIN and GND.

DRVCC

Gate Driver Power Supply Pin. The gate drivers are powered from DRVCC. Connect

DRVCC to INTVCC by a separate trace to the INTVCCbypass capacitor.

BSTVCC

Bootstrap Diode Anode Connection Pin. Place an optional external Schottky diode

between the BSTVCC and BOOST pins to bypass most of the 7Ω switch resistance

between DRVCC and BOOST.

EXTVCC

External Power Input to an Internal LDO Regulator Connected to DRVCC. This LDO

regulator supplies INTVCC power, bypassing the internal VIN LDO regulator whenever

EXTVCC exceeds the EXTVCC switchover voltage. See the EXTVCC connection in the Power

and Bias Supplies (VIN, EXTVCC, DRVCC, and INTVCC) section and INTVCC Regulators

(OPTI-DRIVE) section. Do not exceed 30 V on EXTVCC. Connect EXTVCC to GND if the

EXTVCC LDO regulator is not used.

INTVCC

Output of the Internal LDO Regulator. The INTVCC voltage regulation point is set by the

DRVSET pin. INTVCC must be decoupled to GND with a 4.7µF to 10µF ceramic or other

low equivalent series resistance (ESR) capacitor.

12, 13

High Current Gate Driver for Bottom field-effect transistor (FET). BG pulls up to DRVCC

and pulls down to GND. Tie the BG directly to the bottom FET gate for maximum gate

drive transition speed. Tie a resistor between BG and the bottom FET gate to adjust the

gate slew rate. Tie the BG pins together as close as possible.

BOOST

Bootstrapped Supply to the Top Side Floating Driver. Connect a capacitor between the

BOOST and SW pins. An internal switch provides power to the BOOST pin from DRVCC

when the bottom FET turns on. The voltage swing at the BOOST pin is from DRVCC to

(VIN + DRVCC).

Switch Node Connection to Inductor.

16, 17

High Current Gate Driver for Top FET. TG pulls up to BOOST and pulls down to SW. Tie

TG directly to the top FET gate for maximum gate drive transition speed. Tie a resistor

between TG and the top FET gate to adjust the gate slew rate. Tie the TG pins together

as close as possible.

PGOOD

Power Good Open-Drain Logic Output. PGOOD is pulled to GND when the voltage on

VFB is not within ±10% of its set point.

ILIM

Current Comparator Sense Voltage Range Input. Tying ILIM to GND or INTVCC or floating

ILIM sets the maximum current sense threshold to one of three different levels (25mV,

75mV, and 50mV, respectively).

ITH

Error Amplifier Output and Switching Regulator Compensation Point. The current

comparator trip point increases with this control voltage.

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