ADPL74101 datasheet(19/49 Pages) AD

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Data Sheet

ADPL74101

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Rev. 0

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THEORY OF OPERATION

Main Control Loop

The ADPL74101 is a synchronous controller using a constant-frequency, peak-current mode architecture. During

normal operation, the external top FET turns on when the clock sets the set/reset (SR) latch, causing the inductor

current to increase. The main switch turns off when the main current comparator, ICMP, resets the SR latch. After the

top FET is turned off each cycle, the bottom FET turns on, which causes the inductor current to decrease until either

the inductor current starts to reverse, as indicated by the current comparator (IR), or the beginning of the next clock

cycle.

The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which

is the error amplifier (EA) output. The error amplifier compares the output voltage feedback signal at the VFB pin

(which is generated with an external resistor divider connected across the output voltage, VOUT, to GND) to the

internal 0.8V reference voltage. When the load current increases, it causes a slight decrease in VFB relative to the

reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load

current.

Power and Bias Supplies (V

IN, EXTVCC, DRVCC, and INTVCC)

The INTVCC pin supplies power for the top and bottom FET drivers and most of the internal circuitry. The supply for

the FET drivers is derived from the DRVCC pin, which must be tied to the INTVCCpin to supply power to the gate drivers.

LDO linear regulators are available from both the VIN pin and EXTVCC pin to provide power to INTVCC, which can be

programmed from 4V to 5.5V through control of the DRVSET pin. When the EXTVCC pin is tied to a voltage below its

switchover voltage, the VIN LDO regulator supplies power to INTVCC. If EXTVCC is taken above its switchover voltage,

the VIN LDO regulator turns off, and the EXTVCC LDO regulator turns on. When enabled, the EXTVCC LDO regulator

supplies power to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high-efficiency external

source, such as the ADPL74101 switching regulator output.

High-Side Bootstrap Capacitor

The top FET driver is biased from the floating bootstrap capacitor (CB), which normally recharges through an internal

switch between BOOST and DRVCC whenever the bottom FET turns on. The internal switch is high impedance when

the bottom FET is off, preventing the bootstrap capacitor from overcharging when SW rings below GND during the

dead times.

If the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the

top FET continuously. The dropout detector detects this event and forces the top FET off and the bottom FET on for

a short time every tenth cycle to allow CB to recharge, resulting in a 99% duty cycle at 370kHz operation and

approximately 99% duty cycle at 1MHz operation. If the bootstrap capacitor voltage falls below approximately 75%

of the INTVCC voltage, the boost refresh pulses increase to every fourth cycle to deliver more charge to CB, resulting

in slightly lower duty cycles in dropout.

Dead Time Control

The ADPL74101 provides dead-time control, meaning the driver logic waits for the bottom FET to turn off before

turning on the top FET, and vice versa. Dead-time control results in a fixed dead-time of 20ns.

ADPL74101 Datasheet(PDF) 19 Page - Analog Devices

ADPL74101 Datasheet(HTML) 19 Page - Analog Devices

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