ADPL74101 datasheet(41/49 Pages) AD

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Data Sheet

ADPL74101

analog.com

Rev. 0

41 of 49

Connect the INTVCC decoupling capacitor close to the IC, between the INTVCC and the power GND pin. This

capacitor carries the current peaks of the FET drivers. Place an additional 1μF ceramic capacitor between

the DRVCC and GND pins to improve noise performance.

Keep the switching node (SW), top gate nodes (TG), and boost node (BOOST) away from sensitive small

signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes exhibit large,

and fast-moving signals. Therefore, keep the nodes on the output side of the ADPL74101 and ensure they

occupy the minimum PCB trace area.

Use a modified star ground technique: a low-impedance, large-copper-area central grounding point on the

same side of the PCB as the input and output capacitors, with tie-ins to the bottom of the INTVCC decoupling

capacitor, the bottom of the voltage feedback resistive divider, and the GND pin of the IC.

Figure 41. Branch Current Waveforms

PCB Layout Debugging

Use a DC to 50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output

switching node (the SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output

voltage as well. Check for proper performance over the operating voltage and current range expected in the

application. The frequency of operation is maintained over the input voltage range down to dropout and until the

output load drops below the low current operation threshold, typically 25% of the maximum designed current level

in Burst Mode operation.

The duty cycle percentage is maintained from cycle to cycle in a well-designed, low-noise PCB implementation.

Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage-sensing inputs

or inadequate loop compensation. Overcompensation of the loop can be used to tame an improper PCB layout if

regulator bandwidth optimization is not required.

Reduce the VIN from its nominal level to verify the operation of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate

whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with

high input voltages and low output currents, check for capacitive coupling between the BOOST, SW, TG, and possibly

BG connections and the sensitive voltage and current pins. Place the capacitor across the current-sensing pins next

to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high-frequency

capacitive coupling. If problems are encountered with high-current output loading at lower input voltages, look for

inductive coupling between CIN, the top FET, and the bottom FET components to the sensitive current and voltage

RL1

RSENSE

VOUT

COUT

VIN

CIN

RIN

BOLD LINES INDICATE HIGH SWITCHING

CURRENT. KEEP LINES TO A MINIMUM LENGTH.

ADPL74101 Datasheet(PDF) 41 Page - Analog Devices

ADPL74101 Datasheet(HTML) 41 Page - Analog Devices

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