ADPL74101 datasheet(38/49 Pages) AD

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Data Sheet

ADPL74101

analog.com

Rev. 0

38 of 49

Checking Transient Response

To check the regulator loop response, examine the load current transient response. Switching regulators take several

cycles to respond to a step in the DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal

to ΔILOAD × ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charging or discharging COUT,

generating a feedback error signal that forces the regulator to adapt to the current change and return VOUT to its

steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which

indicates a stability problem.

OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance

and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides

a DC-coupled and AC-filtered closed-loop response test point. The dc step, rise time, and settling at this test point

reflect the closed-loop response. Assuming a predominantly second-order system, the phase margin and/or

damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH external components that are shown in Figure 1, Figure 42,

Figure 44, and Figure 46 provide an adequate starting point for most applications.

The ITH series compensation resistor (RC) to compensation capacitor (CC) filter sets the dominant pole-zero loop

compensation. The values can be modified slightly (from 0.5 times to 2 times their initial values) to optimize the

transient response when the final PCB layout is done, and the particular output capacitor type and value are

determined. The output capacitors need to be selected because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80% of the full load current, with a rise time of 1μs to 10μs,

produces output voltage and ITH pin waveforms that give a sense of the overall loop stability without breaking the

feedback loop.

Placing a power FET directly across from the output capacitor, and driving the gate with an appropriate signal

generator, is a practical way to produce a realistic load-step condition. The initial output-voltage step resulting from

the step change in output current may not be within the bandwidth of the feedback loop. Therefore, this signal

cannot be used to determine phase margin. For this reason, it is better to look at the ITH pin signal, which is in the

feedback loop and is the filtered and compensated control loop response. The gain of the loop increases by

increasing RC, and the bandwidth of the loop increases by decreasing CC. If RC increases by the same factor as CC

decreases, the zero frequency remains unchanged, keeping the phase shift the same in the most critical frequency

range of the feedback loop. The output-voltage settling behavior is related to the stability of the closed-loop system

and demonstrates the actual overall supply performance.

A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this sudden step change in output voltage, if the load switch

resistance is low and it is driven quickly.

If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time must be controlled so that the load rise time is

limited to approximately CLOAD × 25μs/μF. Therefore, a 10μF capacitor requires a 250μs rise time, limiting the charging

current to about 200mA.

ADPL74101 Datasheet(PDF) 38 Page - Analog Devices

ADPL74101 Datasheet(HTML) 38 Page - Analog Devices

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