ADPL74101 datasheet(40/49 Pages) AD

40 / 49 page

Data Sheet

ADPL74101

analog.com

Rev. 0

40 of 49

Due to the high current in this application, two FETs may be needed in parallel to more evenly balance the

dissipated power and to lower the RDS(ON). Be sure to select logic-level threshold MOSFETs, because the gate

drive voltage is limited to 5.5V (INTVCC).

Select the input and output capacitors. CIN is chosen for an RMS current rating of at least 10A (IOUT/2, with

margin) at the temperature. COUT is chosen with an ESR of 3mΩ for low output ripple. Multiple capacitors

connected in parallel may be required to reduce the ESR to this level. The output ripple in continuous mode

is highest at the maximum input voltage. The output voltage ripple (VORIPPLE) due to ESR is approximately

given by Equation 31, as follows:

VORIPPLE = ESR × ∆IL = 3mΩ × 6A =18mVP−P

(31)

On the 3.3V output, 18mVP-P is equal to 0.55% of the peak-to-peak voltage ripple.

Determine the bias supply components. Because the regulated output is not greater than the EXTVCC

switchover threshold, it cannot be used to bias INTVCC. However, if another 5V supply is available, connect

that supply to EXTVCC to improve efficiency. For a 6.7ms soft start, select a 0.1μF capacitor for the TRACK/SS

pin. As a first pass estimate for the bias components, select the INTVCC capacitance (CINTVCC) = 4.7μF and CB =

0.1μF.

Determine and set application-specific parameters. Set the MODE pin based on the trade-off of light-load

efficiency and constant-frequency operation. Set the PLLIN/SPREAD pin based on whether a fixed, spread-

spectrum, or phase-locked frequency is desired. The RUN pin can be used to control the minimum input

voltage for regulator operation, or it can be tied to VIN for always-on operation. Use ITH compensation

components from the typical applications as a first guess, check the transient response for stability, and

modify as necessary.

PCB Board Layout Checklist

Figure 41 shows the current waveforms present in the various branches of the synchronous regulators operating in

the continuous mode.

When laying out the PCB, use the following checklist to ensure the device operates properly.

Route the BG traces together and connect them as close as possible to the bottom FET gate. If using gate

resistors, connect the resistor connections to the FET gate as close as possible to the FET. Connecting the

BG farther from the bottom FET gate can cause inaccuracies in the dead-time control circuit of the

ADPL74101. Route the TG traces together and connect them as close as possible to the top FET gate.

The combined IC GND pin and the GND return of CINTVCCmust return to the combined COUT negative terminals.

The path formed by the top N-channel FET and the CIN capacitor must have short leads and PCB trace

lengths. Connect the output capacitor’s negative terminals as close as possible to the negative terminals of

the input capacitor by placing the capacitors next to each other and away from the loop.

Connect the ADPL74101 VFB pin resistive dividers to the positive terminals of COUT and the signal GND. Place

the divider close to the VFB pin to minimize noise coupling into the sensitive VFB node. The feedback resistor

connections must not be along the high-current input feeds from the input capacitors.

Route the SENSE− and SENSE+ leads together with minimum PCB trace spacing. Route these traces away

from the high-frequency switching nodes on an inner layer, if possible. The filter capacitor between SENSE+

and SENSE− must be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections

at the sense resistor.

ADPL74101 Datasheet(PDF) 40 Page - Analog Devices

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