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ADPL74101 Datasheet(PDF) 11 Page - Analog Devices |
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ADPL74101 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 49 page ![]() Data Sheet ADPL74101 analog.com Rev. 0 11 of 49 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 3. Pin Descriptions PIN NAME DESCRIPTION 1 PLLIN/ SPREAD External Synchronization Input to Phase Detector/Spread Spectrum Enable. When an external clock is applied to PLLIN/SPREAD, the phase-locked loop forces the rising TG signal to synchronize with the rising edge of the external clock. When not synchronizing to an external clock, tie this input to INTVCC to enable spread spectrum dithering of the oscillator, or to GND to disable spread spectrum dithering. 2 MODE Mode Select Input. This input determines how the ADPL74101 operates at light loads. Connect the MODE to GND to select the Burst Mode operation. An internal 100kΩ resistor to GND also invokes Burst Mode operation when MODE is floating. Connect MODE to INTVCC to force continuous inductor current operation. Tying MODE to INTVCC through a 100kΩ resistor selects the pulse skipping operation. 3 FREQ Frequency Control Pin for the Internal Voltage-Controlled Oscillator (VCO). Connect FREQ to GND for a fixed frequency of 370kHz. Program frequencies between 100kHz and 1MHz by using a resistor between FREQ and GND. Minimize the capacitance on FREQ. 4 TRACK/SS External Tracking/Soft Start Input. TRACK/SS regulates the VFB voltage to the lesser of 0.8V or the voltage on the TRACK/SS pin. An internal 12µA pull-up current source is connected to TRACK/SS. A capacitor to GND at TRACK/SS sets the ramp time to the final regulated output voltage. The ramp time is equal to 1ms for every 12.5nF of capacitance. Alternatively, a resistor divider on another voltage supply connected to TRACK/SS allows the output to track the other supply during startup. 5 GND Ground. This pin must be soldered to the printed circuit board (PCB) GND. 9 10 TOP VIEW (Not to Scale) ADPL74101 11 12 13 14 28 27 26 25 24 23 6 5 4 3 2 1 PLLIN/SPREAD MODE FREQ TRACK/SS GND VPRG VIN DRVCC SENSE+ VFB ITH ILIM PGOOD TG TG SW 29 GND 7 8 17 18 19 20 21 22 16 15 NOTES 1. THE EXPOSED PAD (PIN 29) MUST BE SOLDERED TO PCB GROUND FOR RATED ELECTRICAL AND THERMAL PERFORMANCE. |
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