LAN9211 datasheet(33/146 Pages) SMSC

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX

Datasheet

SMSC

LAN9211

Revision 1.93 (11-27-07)

DATASHEET

Note: The TX checksum preamble must be DWORD-aligned (i.e., the two least significant bits of the

Data Start Offset fields in TX Command “A” must be zero). Any valid buffer end alignment

setting can be used.

Note: Software applications must stop the transmitter and flush the TX data path before changing the

state of the TXCOE_EN bit. However, the CK bit of TX Command ‘B’ can be set or cleared on

a per-packet basis.

3.6.2.1

TX Checksum Calculation

The TX checksum calculation is performed using the same operation as the RX checksum shown in

Section 3.6.1.1, with the exception that the calculation starts as indicated by the preamble, and the

transmitted checksum is the one’s-compliment of the final calculation.

3.7

Host Bus Operations

3.7.1

Bus Writes

The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD

transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot

change during a sixteen bit write). No ordering requirements exist. The processor can access either

the low or high word first, as long as the next write is performed to the other word. If a write to the

same word is performed, the LAN9211 disregards the transfer.

3.7.2

Bus Reads

The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD

transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot

change during a sixteen bit read). No ordering requirements exist. The processor can access either

the low or high word first, as long as the next read is performed from the other word. If a read to the

same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The

LAN9211 will reset its read counters and restart a new cycle on the next read.

3.7.3

Mixed Endian Support

In order to allow flexibility with a range of designs, the LAN9211 supports mixed endian Data FIFO

accesses. The LAN9211 provides the ability to select Data FIFO endianess separately for accesses

through the Data FIFO ports (addresses 00h-3Ch) or using the FIFO_SEL input signal. This is

accomplished via the FPORTEND and FSELEND bits of the HW_CFG—Hardware Configuration

The FPORTEND bit determines the endianess of RX and TX Data FIFO host accesses made through

the Data FIFO port addresses (00h-3Ch). When FPORTEND is cleared, Data FIFO port accesses

utilize little endian byte ordering. When FPORTEND is set, Data FIFO port accesses utilize big endian

byte ordering.

The FSELEND bit determines the endianess of RX and TX Data FIFO host accesses when using the

FIFO_SEL signal. When FSELEND is cleared, FIFO_SEL accesses utilize little endian byte ordering.

When FSELEND is set, FIFO_SEL accesses utilize big endian byte ordering.

In addition to mixed endian support, the LAN9211 provides a word swap function, as described in

Section 3.7.4. The word swap function combined with the endianess select bits described above

determines how the Data/Status FIFO’s and CSR host access byte ordering is applied. Table 3.8

describes the various operation modes of the endianess and word swap ordering logic. Figure 3.3

illustrates the FIFO access byte ordering under various endianess and word swap settings. Refer to

Section 3.7.4 for additional details.

LAN9211 Datasheet(PDF) 33 Page - SMSC Corporation

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