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LAN9211 Datasheet(PDF) 38 Page - SMSC Corporation

Part # LAN9211
Description  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
PDF  146 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9211 Datasheet(HTML) 38 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
Revision 1.93 (11-27-07)
38
SMSC
LAN9211
DATASHEET
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9211
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3.4, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an
EEPROM Read or Write operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
3.9.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 103 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
Figure 3.4 EEPROM Access Flow Diagram
Idle
Write Data
Regis ter
Write
Command
Regis ter
Read
Command
Regis ter
Bus y Bit = 0
Idle
Write
Command
Regis ter
Read
Command
Regis ter
Read Data
Regis ter
Busy Bit = 0
EEPRO M W rite
EEPRO M Read



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