LAN9211 datasheet(34/146 Pages) SMSC

34 / 146 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX

Datasheet

Revision 1.93 (11-27-07)

SMSC

LAN9211

DATASHEET

Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess

select bits.

3.7.4

Word Swap Function

In addition to mixed endian functionality, the LAN9211 supports a Word Swap Function. This feature

is controlled by the Word Swap Register, which is described in Section 5.3.17, "WORD_SWAP—Word

Swap Control," on page 98. This register affects how words on the data bus are written to or read from

the Control and Status Registers and the Transmit and Receive Data/Status FIFOs.

Both the word swap function and the mixed endian control bits contain the ability to change the byte

ordering of host data path accesses. Figure 3.2 illustrates the order in which the word swap and

endianess select logic is applied within the LAN9211. Logically, the endian control logic is applied after

the word swap logic for write operations, and before the word swap logic for read operations.

Data path operations for the various supported endianess and word swap configurations are illustrated

in Figure 3.3. Table 3.8, "Endian Ordering Logic Operation" illustrates the byte ordering applied by the

endian logic for each type of host access. This figure and table assume an internal byte ordering of 3-

2-1-0, where ‘3’ is the most significant byte (data[31:24]) and ‘0’ is the least significant byte (data[7:0]).

Figure 3.2 LAN9211 Host Data Path Diagram

"W ORD S W AP"

Logic

FIFO Port Endian O rdering

Logic

RX /TX Data FIFO Port

A ccess (addresses 00h to

3C h)

D irect FIFO A ccess E ndian

O rdering Logic

RX/TX Data FIFO Direct

A ccess

(FIFO _SE L = 1)

CSRs and S tatus FIFO s

FPO R TEN D

(H W _C FG [29])

FSELEN D

(H W _C FG [28])

D[15:0]

(H ost D ata B us)

W O RD_S W AP

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